Semiconductor device with multilayer silicon oxide silicon nitride dielectric
AssigneeHitachi, Ltd.
InventorsYuzuru Ohji, Osamu Kasahara, Yoshitaka Tadaki, Hiroko Kaneko, Toshiyuki Mine, Kunihiro Yagi
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AssigneeHitachi, Ltd.
InventorsYuzuru Ohji, Osamu Kasahara, Yoshitaka Tadaki, Hiroko Kaneko, Toshiyuki Mine, Kunihiro Yagi
Estimating the term…
A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).
A capacitor integral with a solid state device manufactured with the process of:
A capacitor integrally constructed with a semiconductor device, the capacitor comprising:
A solid state device comprising:
A capacitor integrally constructed with an MOS transistor comprising:
A solid state device comprising:
Dependencies are inferred from the claim text.