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US 4,906,994 AGranted
Multi-stage integrated decoder device
AssigneeSiemens Aktiengelsellschaft
InventorsKurt Hoffmann, Rainer Kraus, Oskar Kowarik, Manfred Paul
Life of this patent
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Abstract
A multi-stage integrated decoder device has a special function which facilitates the simultaneous activation of a plurality and as many as all of its outputs. When it is used as a bit line decoder it is thus possible to activate a plurality and as many as all of the bit lines (including any redundant bit lines) of a block of storage cells of a semiconductor memory.
Claims7
Multi-stage, integrated decoder device, comprising:
- a preliminary decoder device having a selection preliminary decoder and internal preliminary decoder units each being in the form of one-from-n decoders, said internal preliminary decoder units including outputs supplying output signals:
- means for supplying a test-enable signal to each of said internal preliminary decoder units deactivating all of said output signals of all of said internal preliminary decoder units;
- a main decoder device receiving output signals from said preliminary decoder device and having a plurality of selection decoders and internal decoders, said selection decoders having outputs and transfer transistors with source terminals:
- and
- first and second potential lines each having one of two mutually-complementary logic levels independently of one another:
- a first half of said outputs of each of said selection decoders each being connected through the source terminals of a respective one of said transfer transistors to said first potential line, and a second half of said outputs of each of said selection decoders each being connected through the source terminals of a respective one of said transfer transistors to said second potential line.
3 more elements
Multi-stage, integrated decoder device, comprising:
- a preliminary decoder device having a selection preliminary decoder and internal preliminary decoder units each being in the form of one-from-n decoders, said internal preliminary deoder units including outputs supplying output signals;
- means for supplying a test-enable signal to each of said internal preliminary decoder units deactivating all of said output signals of all of said internal preliminary decoder units;
- a main decoder device receiving output signals from said preliminary decoder device and having a plurality of selection decoders and internal decoders, said selection decoders having outputs and transfer transistors with source terminals:
- and
- a plurality of potential lines each having one of two mutually-complementary logic levels independently of one another;
- at least one group of said outputs of each of said selection decoders each being connected through the source terminals of a respective one of said transfer transistors to one of said potential lines.
3 more elements
Multi-stage, integrated decoder device, comprising:
- a preliminary decoder device having a selection preliminary decoder and internal preliminary decoder units each being in the form of one-from-n decoders, said internal preliminary decoder units including outputs supplying output signals:
- means for supplying a test-enable signal to each of said internal preliminary decoder units deactivating all of said output signals of all of said internal preliminary decoder units;
- a main decoder device receiving output signals from said preliminary decoder device and having a plurality of selection decoders and internal decoders, said selection decoders having outputs and transfer transistors with source terminals;
- and
- a potential line having one of two mutually-complementary logic levels;
- each of said outputs of each of said selection decoders being connected through the source terminal of a respective one of said transfer transistors to said potential line.
3 more elements
Dependencies are inferred from the claim text.