Digital phase locked loop circuit

A digital phase locked loop circuit comprising:

• sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than the bit rate of a transmission channel;
• operation means for arithmetically operating, by using data at a plurality of successive sampling points, an average phase of a point where the reproduced signal crosses a reference level relative to a predetermined sampling point, for a time period defined by successive sampling points;
• phase locked loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using the average phase output from said operation means;
• phase error detecting means located outside a phase locked loop by said phase locked loop and for obtaining the low frequency components of the phase error on the basis of the operation result by said operation means;
• and
• error correction means for correcting the phase of an input signal to said phase locked loop means by using the low frequency component of phase error derived from said phase error correcting means.

A digital phase locked loop circuit comprising:

• sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than a bit rate of a transmission channel;
• first operation means for obtaining a phase difference between a point where the reproduced analog signal crosses a reference level and a predetermined sampling point, in an interval between two successive sampling points;
• second operation means for obtaining an average of the phase differences obtained by said first operation means;
• and
• phase lock loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using the average obtained by said second operating means.

A digital phase locked loop circuit comprising:

• sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than a bit rate of a transmission channel;
• operation means for obtaining a phase of a point where the reproduced signal crosses a reference level relative to a predetermined sampling point when the reproduced analog signal crosses the reference level at one point, and for obtaining an average phase of points where the reproduced analog signal crosses the reference level relative to each predetermined sampling point when the reproduced analog signal crosses the reference level at a plurality of points, said operation means obtaining the phase or average phase in an interval between successive three or more sampling points;
• and
• phase lock loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using data obtained by said operating means.