Level shift circuit for converting a signal in an ecl level into a signal in a cmos logic level
AssigneeKabushiki Kaisha Toshiba
InventorTetsuya Iida
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Abstract
A level shift circuit is made up of a capacitor, a MOS inverter, and a bias circuit for applying a bias voltage to an input node of the MOS inverter. A first electrode of the capacitor is connected to an output stage of an ECL circuit, while a second electrode to the input node of the MOS inverter. The output node of the MOS inverter is coupled with an input stage of a CMOS circuit. An output signal of the ECL circuit is capacitively coupled with the input node of the MOS inverter so that it is superposed onto a bias voltage being supplied from the bias circuit. A level of this signal is shifted to a CMOS logic level by the MOS inverter, and then applied to the input stage of the CMOS circuit.
Claims17
A level shift circuit for converting a signal in an ECL level into a signal in a CMOS logic level, comprising:
- capacitor means coupled at a first electrode with an output stage of an ECL circuit;
- a MOS inverter connected at an input node to a second electrode of said capacitor means and at an output node to an input stage of a CMOS circuit;
- and
- bias means for applying a bias voltage to the input node of said MOS inverter.
Dependencies are inferred from the claim text.