Low power logic array device

The logic array device of claim 13 wherein said selecting means comprises

• a plurality of pairs of transistors, each pair having an input receiving an output signal from said array or from a signal storage element, only one of said pairs transmitting said output signal at its input to an output, wherein each pair of transistors includes a first high speed transistor with a threshold in a range from 0.6 to 0.8 volts and a second pull-up transistor with a threshold in a range from 0.1 to 0.2 volts, each transistor having a gate receiving a selection control signal.

In a logic array device of the type having at least one array of AND gates, at least one OR gate having a plurality of inputs connected to outputs of said AND gates, at least one flip-flop receiving an output from said OR gate, means for selecting an OR gate output or a flip-flop output for transmission to an output pin, and means for communicating with said selecting means for driving said output pin, the improvement in combination therewith comprising,

• means for detecting changes in logic states of inputs to said AND gates, said detecting means generating a detection signal in response thereto,
• means responsive to said detection signal for generating an AND array enable signal and an OR array enable signal, said AND gates and OR gates being connected to a power supply via associated pull-up elements, said pull-up elements being activated by said enable signals, whereby said AND gates and said OR gates are in an enabled state for predetermined time periods after said changes in logic states are detected and in a disabled state during all other time periods, and
• means for temporarily storing at least one output signal from each OR gate while said AND gates and said OR gates are disabled.