Logic circuit using bipolar complementary metal oxide semiconductor gate and semiconductor memory device having the logic circuit

A logic circuit for improving a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate driven by first and second power source voltages, said logic circuit coupled to a third power source voltage and comprising:

• a bipolar CMOS gate including a CMOS gate and output stage bipolar transistors for receiving an input signal through said CMOS gate, said CMOS gate and said output stage bipolar transistors being driven by the first and second power source voltages, the first power source voltage being higher than the second power source voltage, said output stage transistors outputting a signal as an output signal of said bipolar CMOS gate;
• and
• a p-channel MOS transistor having a gate coupled to said output stage transistor, and supplied with the output signal of said bipolar CMOS gate, said p-channel MOS transistor having a source supplied with the third power source voltage, and a drain for providing an output signal of said logic circuit, the third power source voltage being a predetermined value lower than the first power source voltage and higher than the second power source voltage.