Buffer circuit with load sensitive transition control

Abstract

A buffer circuit particularly suited for driving the output pad of an integrated circuit, characterized in its provision of features which limit the rate of change of current flow in the power supply and ground lines to reduce noise. The circuit features feedback responsive compensation for variations in the capacitive load on the pad. In one form, the circuit includes a feedback capacitor between the pad and the control gate of the output transistor pulling the pad. The control gate of such pulling output driver transistor is, under one operational condition, provided with a voltage which increases at a limited rate during current enablement. The steady-state enablement of the output driver transistor is established later by a circuit logically responsive to the voltage on the output pad. The output driver transistor is subject to rapid disablement in response to a pulling of the control gate by a high speed and drive capacity transistor. In a preferred arrangement the circuit includes tri-state operation capability.

Dependencies are inferred from the claim text.