US 4,906,591 AGranted

Method of manufacturing a semiconductor device having an electric contact portion

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorYoshinori Okumura

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Abstract

In a method of manufacturing a semiconductor device having an electric contact, semiconductor regions (9) as a source or drain region of a MOS transistor, having a conductivity type opposite to that of a semiconductor substrate (1) are formed selectively on the substrate. An insulating layer (10) is formed on the substrate (1) to expose only a surface of each semiconductor region (9). Impurity ions of the conductivity type opposite to that of the substrate (1) are implanted into the exposed surface of each region (9). After that, a polycrystal silicon layer (13) is formed on the surface of each region (9) implanted with the impurity ions and on the insulating layer (10). Further, impurity ions of the conductivity type opposite to that of the substrate (1) are further implanted into the polycrystal silicon layer (13). The condition of implanting the impurity ions into the polycrystal silicon layer (13) is set by controlling implantation energy to enable the maximum point of concentration distribution of the impurity ions in a direction perpendicular to the surface of the substrate (1) to be distant from a position of the interface between the polycrystal silicon layer (13) and the substrate (1) by a dimension corresponding to a standard deviation of the concentration distribution of the impurity ions toward the polycrystal silicon layer (13).

Claims11

Dependent claims

A method of manufacturing a semiconductor device having an electric contact, comprising the steps of:

preparing a semiconductor substrate (1) having a main surface and having a predetermined concentration of impurity of a conductivity type,
selectively forming semiconductor regions (9) of conductivity type opposite to that of said semiconductor substrate (1), spaced from each other on said semiconductor substrate,
forming an insulating layer (10) over said semiconductor substrate,
selectively removing said insulating layer (1) to expose at least a surface of each said semiconductor region (9),
implanting impurity ions of the conductivity type opposite to that of said semiconductor substrate (1) into the exposed surface of each of said semiconductor regions (9),
forming a polycrystal silicon layer (13) over the exposed surface of said semiconductor region (9) and said insulating layer (10),
implanting impurity ions of the conductivity type opposite to that of said semiconductor substrate (1) into said polycrystal silicon layer (13), wherein
said step of implanting the impurity ions into said polycrystal silicon layer (13) is executed by controlling implantation energy to set a maximum point of concentration distribution of said impurity ions in a direction perpendicular to said main surface to be at a position distant from an interface between said polycrystal silicon layer (13) and said semiconductor substrate (1) by a distance corresponding to a standard deviation of said concentration distribution toward said polycrystal silicon layer (13), and
annealing said polycrystal silicon layer (13) in a vicinity of said semiconductor substrate (9) whereby
an electric contact portion (11) is formed between each said semiconductor regions (9) and said polycrystal silicon layer (13).

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/283,804Filed 6 Dec 1988
Priority: JP 62-31780814 Dec 1987
Granted: 6 Mar 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10P 32/302
Diffusion for doping of conductive or resistive layers: doping polycrystalline silicon or amorphous silicon layers
H10D 64/0113
To Group IV semiconductors: the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
H10P 32/1414
From or through or into an external applied layer, e.g. photoresist or nitride layers: the applied layer being silicon, silicide or SIPOS, e.g.…
H10P 32/171
Characterised by the semiconductor material: being group IV material