US 4,906,585 AGranted

Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches

AssigneeSiemens Aktiengesellschaft

InventorsFranz Neppl, Carlos-Alb Mazure-Espejo, Christoph Zeller

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Abstract

A double well CMOS process wherein the wells are separated by insulating trenches introduced into a semiconductor substrate, the position of the insulating trench along the isotropic under-etching in a silicon oxide layer employed together with a silicon nitride layer used as a masking layer in the implantation of the well which is first implanted. The trench itself is produced by anisotropic etching with silicon oxide masks used in the well implantations as etching masks. The trench width is defined with the isotropic etching and the trench depth is defined by the anisotropic etching. In this method, both well implantations and the trench etching are carried out with only one photo-technique. The implantation of the second well and the trench etching are self-adjusting. As a result, minimum spacings between the active zones are provided, and a space saving design is possible. The method is used in LSI CMOS processes.

Claims9

Dependent claims

In a method for the manufacture of neighboring wells with dopants of different conductivity type, the wells being arranged in a common semiconductor substrate and being separated by insulating trenches formed in said substrate comprising the steps of:

generating on the substrate a polysilicon layer;
generating on the polysilicon layer a silicon oxide layer;
generating on the silicon oxide layer a silicon nitride layer;
depositing on the silicon nitride layer a photosensitive resist layer;
utilizing a phototechnique to structure the silicon nitride layer and the silicon oxide layer so that the polysilicon layer is exposed in an area of a well to be implanted first,
utilizing the silicon nitride layer and silicon oxide layer as a masking layer in the implantation of the first well,
after implantation, the silicon oxide layer arranged between the silicon nitride layer and the polysilicon layer is isotropically etched;
and
etching a trench anisotropically utilizing the etched silicon oxide layer as an etching mask, the trench depth being determined by the etching time of said anisotropic etching of the trench etching and the trench width being controlled by the etching time of the isotropic etching of the silicon oxide layer, and forming a layer of silicon oxide to mask said first well for the implantation of a second well.

6 more elements

A method for the manufacture of a double-well transistor assembly comprising the following steps in the order given:

(a) thermally oxidizing a silicon substrate surface and applying a polycrystalline silicon layer on a resultant thermally oxidized silicon substrate surface,
(b) applying a first silicon oxide layer from the vapor phase onto the polycrystalline silicon layer,
(c) applying a first silicon nitride layer from the vapor phase over said first silicon oxide layer,
(d) applying a photoresist structure to mask the p-well regions to be produced in said substrate;
(e) anisotropically etching the first silicon oxide/silicon nitride layers to expose n-well regions,
(f) implanting arsenic, antimony, or phosphorus to generate n-wells in said n-well regions,
(g) isotropically under-etching said first silicon oxide layer to define the position of an insulating trench,
(h) removing said photoresist mask;
(i) forming a second silicon oxide layer by thermal oxidation of a surface of the polycrystalline silicon layer,
(j) depositing a second silicon nitride layer and anisotropically re-etching said second silicon nitride layer so that said second silicon nitride layer remains in the location of the under-etching of said first silicon oxide layer,
(k) forming a third silicon oxide layer by thermal oxidation of the polycrystalline silicon not masked by the first and second silicon nitride layers,
(l) removing said first and second silicon nitride layers and then anisotropically etching said polycrystalline silicon layer using the first silicon oxide layer and the third silicon oxide layer as mask,
(m) performing boron-ion implantation for generating a p-well,
(n) anisotropically etching to remove said second silicon oxide layer in the locations at which insulating trenches are to appear,
(o) anisotropically etching the trenches in the substrate,
(p) removing said first and third silicon oxide layers and remaining polycrystalline layer,
(q) generating a fourth silicon oxide layer on the substrate by thermal oxidation,
(r) thermally driving in dopant atoms implanted in the wells, and
(s) filling said trenches with polycrystalline silicon from the vapor phase, anisotropically re-etching the polycrystalline silicon, and wet-chemically re-etching said fourth silicon oxide layer remaining on said substrate.

16 more elements

A method for the manufacture of a double-well transistor assembly comprising the following steps in the order given:

(a) thermally oxidizing a silicon substrate surface and applying on a resultant thermally oxidized substrate surface a polycrystalline silicon layer,
(b) applying a first silicon oxide layer from the vapor phase onto the polycrystalline silicon layer,
(c) applying a first silicon nitride layer from the vapor phase over said first silicon oxide layer,
(d) applying a photoresist structure to mask the p-well regions to be produced in said substrate,
(e) anisotropically etching the first silicon oxide/silicon nitride layers to expose n-well regions,
(f) implanting arsenic, antimony, or phosphorus to generate n-wells in said n-wells regions,
(g) isotropically under-etching said first silicon oxide layer to define the position of an insulating trench,
(h) removing said photoresist mask,
(i) forming a second silicon oxide layer by thermal oxidation of a surface of the polycrystalline silicon layer,
(j) depositing a second silicon nitride layer and anisotropically re-etching said second silicon nitride layer so that said second silicon nitride layer remains in the location of the under-etching of said first silicon oxide layer,
(k) forming a third silicon oxide layer by thermal oxidation of the polycrystalline silicon not masked by the first and second silicon nitride layers,
(l) removing said first and second silicon nitride layers,
(m) anisotropically etching to remove said second silicon oxide layer in the locations at which insulating trenches are to appear,
(n) anisotropically etching the trenches in the substrate,
(o) applying a further silicon oxide layer on the substrate and etching same back to form an implantation mask,
(p) performing boron-ion implantation for generating a p-well,
(q) removing said first, third, and further silicon oxide layers,
(r) generating a fourth silicon oxide layer on the substrate by thermal oxidation,
(s) thermally driving in dopant atoms implanted in the wells, and
(t) filling said trenches with polycrystalline silicon from the vapor phase, anisotropically re-etching the polycrystalline silicon, and wet-chemically re-etching said fourth silicon oxide layer remaining on said substrate.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/197,663Filed 20 May 1988
Priority: DE 37258394 Aug 1987
Granted: 6 Mar 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0191
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells
H10P 50/691
Using masks for semiconductor materials: for Group IV materials or Group III-V materials
H10P 76/40
Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography: of masks comprising inorganic materials