High speed booster circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMakoto Taniguchi
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Abstract
An output signal line is boosted at first by a first booster circuit using a second power supply. Thereafter, it is boosted by a second booster circuit using a third power supply.
Claims10
A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal line is raised at high speed to approximately the same level as said third voltage level, comprising:
- a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply;
- and
- a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit.
A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal lines is raised at high speed to approximately the same level as said third voltage level, comprising:
- a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply;
- and
- a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit,
- wherein said first booster circuit comprises:
- a first voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage and providing at least said second voltage level in response to an occurrence of said input signal;
- and
- a first transistor interposed between said second power supply and said output signal line which is controlled by the output voltage of said first voltage generation circuit;
- and
- said second booster circuit comprises:
- a second voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage having a level higher than said second voltage level with a slight delay from the generation of the voltage in said first voltage generation circuit;
- and
- a second transistor interposed between said third power supply and said output signal line which is controlled by the output voltage of the second voltage generation circuit.
In a high-speed voltage booster circuit of a type having a bootstrap circuit and a driver circuit for use with a semiconductor integrated circuit, at least said driver circuit having a capacitor, the improvement comprising
- a circuit interposed between said bootstrap circuit and said driver circuit comprising a first transistor and a second transistor connected with series between first and second power supplies, a node between said first and second transistors being connected to an input of said driver circuit, said first transistor having a control electrode connected to a first electrode of said capacitor of said driver circuit and said second transistor having a control electrode connected to an input of said bootstrap circuit.
A high speed booster circuit having a first power supply set at a first voltage level, a second power supply set at a second voltage level which is higher than said first voltage level, a third power supply set at a third voltage level which is higher than said second voltage level, an input signal line and an output signal line wherein the voltage level of said output signal lines is raised at high speed to approximately the same level as said third voltage level, comprising:
- a first booster circuit including a boost capacitor controlled by said input signal for providing a low impedance connection of said output signal line to said second power supply;
- and
- a driver circuit including a second booster circuit responsive to a signal appearing at a terminal of said boost capacitor for providing a low impedance connection of said output signal line to said third power supply and interrupting said low impedance connection of said first booster circuit,
- wherein said first booster circuit comprises:
- a first voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage and providing at least said second voltage level in response to an occurrence of said input signal;
- and
- a first transistor interposed between said second power supply and said output signal line which is controlled by the output voltage of said first voltage generation circuit;
- and
- said second booster circuit comprises:
- a second voltage generation circuit coupled to said first power supply and said second power supply for generating a voltage having a level higher than said second voltage level with a slight delay from the generation of the voltage in said first voltage generation circuit;
- and
- a second transistor interposed between said third power supply and said output signal line which is controlled by the output voltage of the second voltage generation circuit,
- further comprising
- a third transistor for discharge interposed between the gate of said first transistor and said first power supply and responsive to the output of said second voltage generation circuit generating a level higher than said second voltage level.
Dependencies are inferred from the claim text.