US 4,905,258 AGranted

Data circuit-terminating equipment

AssigneeIwatsu Electric Co., Ltd.

InventorsToshimichi Shimatani, Yoshihiro Kawata, Masaharu Kamigaki

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Abstract

There is disclosed a data circuit-terminating equipment (DCE) which connects a start-stop synchronous data terminal equipment (DTE) which is not synchronized with a PCM transmission line having various speeds. Further the DCE can satisfy recommendations of the V25 bis of CCITT. The DCE includes a start-stop synchronizing circuit to deliver a sampled request-to-send signal RS, a sampled send data and to transmit a clear-to-send signal CS to the DTE, a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make the sampled send data match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE. In the DCE satisfying the recommendations, the demapping circuit ANDs a clear-to-send signal and bits indicating the synchronized state to send the clear-to-send signal, and a short line shorting the clear-to-send signal and a carrier detect signal is employed.

Claims22

Dependent claims

A data circuit-terminating equipment for connecting a start-stop synchronous data terminal equipment with a PCM transmission line which can transmit at various transmission rates by means of accommodating data and control signals in a multiframe construction by using at least a PCM synchronization signal and at least a PCM clock, wherein said data circuit-terminating equipment comprises:

start-stop synchronizing means for sampling a request-to-send signal and send data, which are transmitted from said start-stop synchronous data terminal equipment, with a sampling clock of which repetition rate is higher than a repetition rate of said send data in which said sampling clock is synchronized with a standard clock, for delivering said sampled request-to-send signal and said sampled send data, and for transmitting a clear-to-send signal to said start-stop synchronous data terminal equipment corresponding with data volume of said sampled send data to be sent out;
mapping means for mapping said sampled request-to-send signal, said samples send data and control signals from said start-stop synchronizing means in a predetermined procedure and for constructing multiframes to send out a mapped signal;
sending register means for registering said mapped signal to send out at a transmission rate of said PCM transmission line at a timing being determined by said PCM synchronization signal and said PCM clock to said PCM transmission line;
receiving register means for receiving and registering data and control signals of multiframes which are received from said PCM transmission line at said transmission rate and for delivering a signal to-be-demapped at a predetermined timing synchronized with said PCM synchronization signal;
demapping means for demapping said signal to-be-demapped to obtain demapped data and control signals and for delivering said demapped data and control signals to said start-stop synchronous data terminal equipment at a predetermined timing;
PLL means including a phase-locked loop for generating said standard clock which synchronizes with said PCM synchronization signal;
and
timing generating means for generating required timing signals from said standard clock, said PCM synchronizatioan signal and said PCM clock which are supplied to said start-stop synchronizing means, said sending register means, said receiving register means, said mapping means and said demapping means.

5 more elements

A data circuit-terminating equipment for connecting a start-stop synchronous data terminal equipment with a PCM transmission line which can transmit at various transmission rates by means of accommodating data and control signals in a multiframe construction by using at least a PCM clock, wherein said data circuit-terminating equipment comprises:

start-stop synchronizing means for sampling a request-to-send signal and send data, which are transmitted from said start-stop synchronous data terminal equipment, with a sampling clock of which repetition rate is higher than a repetition rate of said send data in which said sampling clock is synchronized with a standard clock, for delivering said sampled request-to-send signal and said sampled send data, and for transmitting a clear-to-send signal to said start-stop synchronous data terminal equipment corresponding with data volume of said sampled send data to be sent out;
mapping means for mapping said sampled request-to-send signal, said sampled send data and control signals, which include at least a clear-to-send signal, from said start-stop synchronizing means in a predetermined procedure and for constructing multiframes to send out a mapped signal;
sending register means for registering said mapped signal to send out at a transmission rate of said PCM transmission line at a timing being determined by said PCM synchronization signal and said PCM clock to said PCM transmission line;
receiving register means for receiving and registering data and control signals of multiframes which are received from said PCM transmission line at said transmission rate and for delivering a signal to-be-demapped at a predetermined timing synchronized with said PCM synchronization signal;
demapping means for demapping said signal to-be-demapped to obtain demapped data and control signals which include at least a carrier detect signal and for delivering said demapped data and control signals to said start-stop synchronous data terminal equipment at a predetermined timing;
PLL means including a phase-locked loop for generating said standard clock which synchronizes with said PCM synchronization signal;
timing generating means for generating required timing signals from said standard clock, said PCM synchronization signal and said PCM clock which are supplied to said start-stop synchronizing means, said sending register means, said receiving register means, said mapping means and said demapping means;
and
shorting means for shorting to make said carrier detect signal from said demapped means into said clear-to-send signal in said mapping means.

6 more elements

Dependencies are inferred from the claim text.