Pipelined error detection and correction apparatus with programmable address trap

An error detection and correction apparatus with programmable address trap comprising in combination:

• means for receiving and holding data signals, said data means receiving data signals from a random access memory,
• means for generating check bits, said check bit means generating a predetermined number of check bits, said check bits are parity bits which are derived from said data signals,
• means for outputting signals, said signal output means operatively connected to said data means and said check bit means to receive said data signals and said check bits therefrom, said signal output means applying said data signals and check bits to said random access memory, said random access memory applying said data signals and check bits to said data means,
• means for error correction, said error correction means receiving said check bits and said data signals from said data means, said error correction means decodes said check bits for signal bit errors, said error correction means will correct a single bit error in said data signals by inverting the error bit in said data signals, said data signals either error free or error corrected, is passed to said signal output means, said error correction means provides an error signal, said error signal is coded to represent either no error, a single bit error, a double bit error, or more than a double bit error,
• an address trap register operatively connected to said signal output means to trap the address of said data signal at which an error occurs, and,
• means for error detection, said error detection means operatively connected to said error correcting means to receive said error signal therefrom, said error detection means decoding said error signal to determine the error state.