Logic module for generating unequiprobable/random patterns for integrated circuits

A logic system for generating an unequiprobable random bit pattern for supporting the self-test of integrated circuits comprising:

• a first logic module including,
• a concatenated series of first and second basic cells having outputs responsive to a plurality of input control signals and connected to operate said first logic module selectively as a normal register, a series shift register, or a feedback shift register in response to said plurality of input control signals,
• a feedback path for minimizing the autocorrelation function of the outputs of said concatenated series of first and second basic cells during operation of said first logic module as a feedback shift register, said feedback path supplying an output of a last basic cell of said concatenated series of first and second basic cells to inputs of a plurality of first basic cells in said concatenated series of first and second basic cells, each of said first basic cells in said plurality of first basic cells including combining logic means having first (A), second (B) and third (C) data inputs for logically combining signals on said data inputs to provide a plurality of Boolean function signals at respective outputs of said combining logic means, at least one of said plurality of Boolean function signals being a combinatorial function having said second (B) and third (C) data inputs as operands, said third (C) data input connected to said feedback path and said second (B) data input accepting an output of an immediately preceding basic cell in said concatenated series of first and second basic cells, said at least one of said plurality of Boolean function signals being supplied for output by each of said first basic cells during operation of said first logic module as a feedback shift register, and
• a combinatorial logic circuit connected to selected data outputs of said concatenated series of first and second basic cells for operating said selected data outputs in accordance with a predetermined Boolean function to provide at an output of said combinatorial logic circuit a bit sequence in which the probability of an occurrence of a logical "1" is defined by said predetermined Boolean function;
• and
• a second logic module connected to said first logic module including,
• selecting means responsive to said input control signals for selectively through-connecting to an output of said selecting means either the output of said last basic cell of said concatenated series of first and second basic cells or said output of said combinatorial logic circuit, and
• a concatenated series of second basic cells responsive to said input control signals and connected to operate as a serial shift register, a first occurring second cell in said concatenated series of second basic cells being connected to receive said output of said selecting means.