Communication system for timing multiplex hybrids

A hybrid time multiplex switching system, in which entering time multiplex signal and outgoing multiplex signals are made up of time frames having fixed length time intervals, each interval carrying a block of words that make up either a packet or a channel, except for a first time interval of each of said frames which contains a frame synchronization block, the entering multiplex signals being applied to a packet time switch using a paragonal conversion and having one input circuit for each of said entering multiplex signals, an input rotation matrix, a packet buffer memory, transfer circuits, an output rotation matrix, a time base clock circuit, a label translation memory circuit and memory file circuit for giving a packet write addresses into the packet buffer memory, each write address being associated with output multiplex signals, each of said input circuits comprising a synchronization circuit capable of recognizing the presence of a frame synchronization block, a file circuit and a word serial to parallel converter, the synchronization circuit of each of said input circuits generating file order data for each time interval in a frame, the order data being transmitted from the input circuits to the input rotation matrix which has an output and generating the said file order data which with identification data of the entering multiplex signal makes up a block identification data which is applied to an address input of a programmable discrimination memory whose output is connected to means for blocking validation signals generated by the first label translation memory to address storage files, outputs of the input rotation matrix being also connected to corresponding buffer memories having write address inputs which receive the block identity data, said buffer memories having read address input connected to the output of a read control memory and outputs of said buffer memories connected to the corresponding inputs of transfer circuits, address input of a third read control memory receiving data from the time base clock circuit and also generating two signals which are applied to a switch control circuit for the transfer circuits and for which the first is connected to means of inhibiting the reading of the storage means.