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US 4,905,195 AGranted
Semiconductor memory
AssigneeHitachi, Ltd.
InventorsMinoru Fukuda, Hideaki Takahashi, June Sugiura, Fumio Tsuchiya, Toshimasa Kihara
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Abstract
An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of this parallel signal action.
Claims27
In a semiconductor memory, the improvement for writing information comprising:
- a memory array having a plurality of data lines, including a plurality of nonvolatile semiconductor memory cells which can be erased and electrically written into;
- external terminal means for receiving serially applied input signals or an input signal to be written into said memory array;
- converter means having an input coupled to said external terminal means and having a plurality of outputs, said converter means responding to said serially applied input signals for converting said input signals into a plurality of parallel produced output signals;
- a plurality of terminals, corresponding in number to the number of outputs of said converter means, being respectively coupled to said outputs of said converter means, and being coupled to the data lines of said memory array;
- transmitting means having an input coupled to said external terminal means and having a plurality of outputs coupled to said terminals, said transmitting means responding to said input signal for controllably transmitting said input signal to one of said terminals;
- an external control terminal for receiving a control signal;
- and
- control means coupled to said converter means and to said transmitting means for selecting either a serial-to-parallel transmission of said serially received input signals through said converter means or transmitting said input signal through said transmitting means to one of said terminals in accordance with said control signal.
5 more elements
In a semiconductor memory, the improvement for writing information comprising:
- a memory array including a plurality of word lines, a plurality of data lines intersecting said word lines, and a plurality of semiconductor nonvolatile memory cells respectively provided at the intersections between said data lines and word lines, wherein said semiconductor nonvolatile memory cells can be erased and electrically written into;
- a plurality of common data lines;
- first selecting means for selecting a word line of said plurality of word lines in accordance with first address signals;
- second selecting means for selecting ones of said plurality of data lines, and for respectively coupling each one of said common data lines selected with corresponding ones of said data lines selected in accordance with second address signals;
- external terminal means for receiving serially applied input signals or an input signal to be written into said memory array;
- external means for receiving a writing voltage;
- a plurality of writing circuits, each having a terminal coupled to said external means and having an input and an output;
- plurality of storage means, each having an input and an output, for temporarily storing respective input signals;
- control means for providing first and second selecting signals;
- third selecting means for sequentially feeding said input signals, via a plurality of signal paths, to the inputs of said plurality of storage means, in accordance with said first selecting signals provided from said control means;
- transmitting means, having an input coupled to said external terminal means and a plurality of outputs respectively coupled to said inputs of said writing circuits, for transmitting said input signal to an input of a corresponding one of said plurality of writing circuits in accordance with said second selecting signals provided from said control means;
- control terminal means for receiving a control signal, said control means being coupled to said control terminal means, to said third selecting means, and to said transmitting means, for providing one of said first and second selecting signals in accordance with said control signal;
- and
- inhibiting means for inhibiting the operation of said plurality of writing circuits and the transmitting of said input signal by said transmitting means,
- wherein said plurality of writing circuits correspond in number to the number of said common data lines and its outputs are respectively coupled to said common data lines, said plurality of storage means correspond in number to the number of said writing circuits and its outputs are respectively coupled to the inputs of said writing circuits for providing said temporarily stored signals to said writing circuits, and wherein there are a greater number of said data lines than the number of said common data lines.
12 more elements
Dependencies are inferred from the claim text.