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US 4,905,194 AGranted
Semiconductor memory device with a circuit for analyzing defects in word-lines
AssigneeKabushiki Kaisha Toshiba
InventorsNobuaki Ohtsuka, Junichi Miyamoto
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Abstract
A semiconductor memory device of the invention includes a memory cell array including a plurality of memory cells, and a row decoder and a column decoder for selecting word-lines and bit-lines, respectively. The semiconductor memory device further includes a plurality of transistors having their gates connected to corresponding word-lines, their sources connected to a fixed potential source, and their drains connected commonly to a predetermined pad.
Claims6
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells;
- a plurality of word-lines, each word-line connected to corresponding memory cells;
- a plurality of bit-lines, each bit-line connected to corresponding memory cells;
- a row decoder connected to the plurality of word-lines for selecting word-lines in accordance with address signals and a column decoder connected to the plurality of bit-lines for selecting bit-lines in accordance with address signals;
- and
- a plurality of transistors connected in parallel between a predetermined potential supply terminal and a pad, each of said plurality of transistors having a gate connected to a corresponding word-line, each of said plurality of transistors being switch-controlled in accordance with a potential of said corresponding word-line.
3 more elements
Dependencies are inferred from the claim text.