US 4,905,192 A · Semiconductor memory cell

Abstract

A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.

Claims7

Dependent claims

A semiconductor memory device comprising:

a memory cell array having a spare memory cell array;
first addressing means for designating an address of said memory cell array;
second addressing means for designating an address of said spare memory cell array, said second addressing means being activated simultaneously with said first addressing means;
drive means for activating a select line designated by each of said first and second addressing means;
a program circuit for generating a predetermined output based on whether said memory cell array has a defect or fault or not;
and
a select circuit responsive to said output from said program circuit for supplying an activation signal delayed by a delay circuit to said designated select line for the selection of said spare memory cell array when there is a fault in said memory cell array.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory cell

Life of this patent

Semiconductor memory cell

Life of this patent

Abstract

Claims7