Microcomputer with built-in EPROM and test mode

A single-chip microcomputer comprising:

• an internal bus;
• a microprocessor coupled to the internal bus for executing information processing in according with a predetermined program;
• an electrically programmable read only memory coupled to the internal bus for storing the predetermined program therein, the electrically programmable read only memory including,
• memory cell means having first memory cells for storing data constituting the predetermined program and at least one second memory cell for storing data for testing, selecting means for selecting one of either the first memory cells or the second memory cell,
• input means for providing data to be written into the memory cell means from the internal bus to the memory cell means, and
• output means for providing data to be read out from the memory cell means to the internal bus,
• wherein the electrically programmable read only memory has a first operating mode in which the electrically programmable read only memory is accessed from the microprocessor, and a second operating mode in which the electrically programmable read only memory is accessed from outside of the single-chip microcomputer, and wherein the second operating mode further includes a test mode in which the selecting means only selects the second memory cell in response to a control signal;
• first control means coupled to the electrically programmable read only memory for controlling whether or not the electrically programmable read only memory is to be operated in the second operating mode;
• first external terminals to which address signals to be applied to the selecting means are applied in the second operating mode;
• second external terminals to which data to be fed to or from the electrically programmable read only memory is applied in the second operating mode;
• and
• second control means coupled to one of the first external terminals and for discriminating whether or not the electrically programmable read only memory is to be operated in the test mode and for providing the control signal to the selecting means when the electrically programmable read only memory is to be operated in the test mode.