US 4,905,188 A · Functional cache memory chip architecture for improved cache access

Abstract

An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write CPU access function which provides an architectural organization for allowing the chip to be used in (1) a fast, "late-select" operation which may be provided with any desired degree of set-associativity while achieving an effective one-cycle write operation, and (2) a cache reload function which provides a highly parallel store-back and reload operation to substantially reduce the reload time, particularly for a store-in cache organization. The cache chip organization and architecture provide a late-select cache having a nearly transparent, multiple word reload by incorporating a Cache-Reload Buffer, a store-back buffer and a load-through function all included on the cache array chip for reloading, and a delayed write-enable for achieving an effective one-cycle write operation. Two separate decoder functions are integrated on the chip, one for cache access for normal read/write operations to and from the CPU and one for cache reload which also provides interim access to data which has been transferred out of main memory to the chip but not yet reloaded into the cache array. These two decoders provide for different accessing modes as required of the CPU or main memory operations.

Claims17

Dependent claims

A VLSI cache memory subsystem including, on-chip a single-port, late-select, cache array organized to be n-way set associative said chip including a plurality of functionally interrelated units on-chip with the cache array which comprise;

(1) means for performing a normal CPU read access operation including means for accessing the chip in a fast, "late-select" mode, which is n-way set-associative, in effectively one memory cycle for a read operation to the CPU, (2) means for performing an internal late-write operation including means for allowing a CPU "write" to one of n accessed words in effectively one cycle, and (3) means for performing a cache reload operation including means for providing a highly parallel multi-word store-back and reload operation to and from main memory, to reduce the reload time for a store-in cache organization, said means for performing the reload operation additionally including means for performing a nearly transparent, multiple word reload and including a Cache-Reload Buffer, a Store-Back Buffer and a load-thru mechanism all included on the chip for reloading,
said system further including two separate decoders integrated on the chip, one actuable for normal single word read/write cache access by the CPU and one actuable for parallel multi-word cache reload, and means to access date in the Cache Reload Buffer which has been transferred out of main memory to the chip but not yet reloaded into the cache array, said two decoders providing two different accessing modes required for CPU or main memory operations.

A late-select VLSI cache memory subsystem chip comprising an array having a single access port and a plurality of functionally related elements entirely mounted on-chip with said array and efficiently interconnected therewith to provide enhanced functionality and speed, said subsystem chip including;

n separate set-associative memory segments in the on-chip cache array,
first addressing/decoding means interfacing the array with the CPU, comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system,
second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array,
means utilizing said first addressing means for a normal cache read/write access, and
means utilizing said second addressing means for memory store-back and cache reload operations,
means for performing a late-write operation which allows a word to be written into the array from the CPU at one of n accessed words within a single memory cycle,
control means including first buffers for interfacing logical words to be accessed to/from the cache and from/to the CPU in a single array access cycle, and
control means including second buffers for interfacing blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle.

5 more elements

n separate set-associative memory segments in the on-chip cache array,
first addressing/decoding means interfacing the array with the CPU, comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next, a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system,
second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array,
said first and second addressing/decoding means including a common portion for selecting a particular row in said array, said row including a multiple word data block for each of the n associative sets in said array,
means utilizing said first addressing means for a normal cache read/write access, and
means utilizing said second addressing means for highly parallel multi-word memory store-back and cache reload operations,
means for performing a late-write operation which allows a word to be written into the array from the CPU at one of n accessed words within a single memory cycle,
control means including first buffers for accumulating logical words to be accessed to/from the cache and from/to the CPU in a single array access cycle, and
control means including second buffers for accumulating blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle,
a late-select mechanism including means for providing a signal to said chip indicating which associative set is required for a particular access.

7 more elements

Dependencies are inferred from the claim text.

Functional cache memory chip architecture for improved cache access

Life of this patent

Functional cache memory chip architecture for improved cache access

Life of this patent

Abstract

Claims17