Self-configuring memory management system with on card circuitry for non-contentious allocation of reserved memory space among expansion cards

A printed circuit board card having terminals electrically connecting with cooperating terminals disposed in one of six slots on a main circuit board of a personal computer system, wherein said main circuit board includes a central processing unit (CPU), a first memory coupled to said CPU to receive addresses of memory locations from said CPU and to provide data to said CPU, a 32-bit address bus being coupled to said CPU to receive addresses from said CPU, and input/output circuitry coupled to said first memory to provide data to said first memory and coupled to said CPU to receive control signals from said CPU, each of said slots being coupled to said 32-bit address bus, said CPU including an address generation means for generating 2.sup.32 different addresses ranging from location $0000 0000 to location $FFFF FFFF, said locations being in hexadecimal notation, each of said slots having a distinct number in said computer system and being coupled to distinct identification line means on said main circuit board, said distinct identification line means comprising four lines each carrying binary values, and wherein said six slots on said main circuit board have distinct numbers $9, $A, $B, $C, $D, and $E each of said slots having its own distinct identification line means providing its own distinct signal identifying the distinct number of the slot, such that a slot having a distinct number $9 is slot $9 and said distinct identification line means coupled to said slot $9 will provide the value $9 to said slot $9, said card comprising a second memory disposed on said card, said second memory being a random access memory and being selectively coupled to said CPU through said 32-bit address to bus to receive addresses of memory locations and to provide data over said address bus, said second memory being coupled to said 32-bit address bus which provides, during a first cycle, an address and receives, during a second cycle, data located at said address, said card further comprising a decoder means coupled to said distinct identification line means for receiving said distinct signal, said decoder means comparing said distinct number to the most significant hexadecimal digit of said address to determine when said distinct number, in hexadecimal, is equal to the most significant hexadecimal digit of said address, said decoder means enabling said second memory to be addressed to provide data when said distinct number, in hexadecimal, is equal to the most significant hexadecimal digit of said address such that, where said distinct number of said slot is X, said second memory is addressed whenever addresses between $X000 0000 and $XFFF FFFF appear on said 32-bit address bus, whereby 256 megabytes of memory space are reserved for said card in said slot, said 256 megabytes of memory space beginning at location $X000 0000 and ending at location $XFFF FFFF.