MOS adder with minimum pass gates in carry line
AssigneeIntel Corporation
InventorSudarshan Kumar
Life of this patent
Estimating the term…
Abstract
A metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals for a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.
Claims12
An MOS partitioned, carry lookahead adder comprising:
- a plurality of groups each generating a group propagate signal and a plurality of sum signals for its respective group, each group having a carry-in terminal and a carry-out terminal;
- said carry-out terminal of one of said groups being coupled to said carry-in terminal of the next of said groups, thereby coupling said groups in series;
- a main lookahead carry line for propagating carry signals having a plurality of sections, each section coupling the carry-out terminals of the nth one of said groups to the carry-in terminals of the n+2 one of said groups in said series;
- and,
- each of said sections of said carry line having a single first transistor with a first region and a second region coupled into one of said sections of said propagate line, such that carry signals propagating along said section pass from said first region to said second region of said first transistor and said carry signals is controllable by the gate of said first transistor, said gate of said first transistor being coupled to receive said group propagate signal for its respective group.
An MOS partitioned, carry lookahead adder comprising:
- a plurality of groups each generating a group propagate signal and a plurality of sum signals for its respective group, each group having a carry-in terminal and a carry-out terminal;
- said carry-out terminal of one of said groups being coupled to said carry-in terminal of the next of said groups, thereby coupling said groups in series;
- a main carry line having a plurality of sections, each section coupling the carry-out terminals of the nth one of said groups to the carry-in terminal of the n+2 one of said groups in said series;
- and
- logic means in each of said groups for decoupling said carry-out terminal of its respective group when said certain propagate signal within said group are at a predetermined level.
An MOS partitioned, carry lookahead adder comprising:
- a plurality of groups each generating a group propagate signal and a plurality of sum signals for its respective group, each group having a carry-in terminal and a carry-out terminal, said carry-out terminal of one of said groups being coupled to said carry-in terminal of the next of said groups, thereby coupling said groups in series;
- each of said groups comprising at least one block, each of said blocks providing a block propagate signal and a plurality of said sum signals for its respective block, each of said blocks having one of said carry-in terminals and one of said carry-out terminals;
- a block carry line extending between said carry-in terminal and said carry-out terminal of each of said blocks, each of said block carry lines including a first transistor disposed in said block carry line for controlling the propagation of carries along said block carry line;
- a main carry line for propagating carry signals having a plurality of sections, each section extending from said carry-out terminal of the nth one of said groups in said series to the carry-in terminal of the n+2 one of said groups in said series, each section of said main propagate line including a second transistor disposed in said section;
- and
- said block propagate signals being coupled to control said first transistors of its respective block and said group propagate signals being coupled to said second transistor of its respective group.
Dependencies are inferred from the claim text.