CMOS cell for logic operations with fast carry
AssigneeCSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
InventorsLuigi Licciardi, Alessandro Torielli
Life of this patent
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Abstract
The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the second consists of a 4-transistor series cirucit, two P-MOS (T3, T4) and two N-MOS (T5, T6) geenrating carry output CoutN complemented when the two operands have equal logic levels.
Claims7
An elementary C-MOS cell for executing logic additions between two operand bits (A,B) with carry propagation, comprising:
- a first EX-OR logic gate (EX2) which receives said operand bits (A,B);
- a first inverter (I1) which receives a carry input (Cin);
- a second inverter (I2) which receives the output of the first EX-OR logic gate (EX2);
- a first transfer gate (T1, T2) which receives at the transfer input the output of said first inverter (I1), and which is controlled by input and output logic levels of said second inverter (I2);
- a second EX-OR logic gate (EX1) which receives input carry (Cin) and the output of said second inverter (I2) and supplies the addition result (S);
- and
- a first pair of series P-MOS transistors (T3, T4) and a second pair of series N-MOS transistors (T5, T6), said first and second pair being connected in series between two reference voltages, the bit of a first operand (A) being brought to the gate of a transistor of both pairs, the bit of a second operand (B) being brought to the gate of the other transistor of both pairs, the common node of said two pairs being connected to the output of said first transfer gate (T1, T2) and supplying the complemented output carry (CoutN), said first transfer gate consisting of a P-MOS transistor (T1) in parallel with an N-MOS transistor (T2), the input of said second inverter (I2) being sent to the gate of an N-MOS transistor and the output of the second inverter to the gate of a P-MOS transistor of the transfer gate.
A multiplying circuit of the parallel-parallel type consisting of elementary cells, which implements the product of two units of data X(i) and Y(j) available in parallel form, and obtains a result in parallel form, each elementary cell executing logic additions between two operand bits and comprising:
- a first EX-OR logic gate (EX2) which receives said operand bits (A, B);
- a first inverter (I1) which receives a carry input (Cin);
- a second inverter (I2) which receives the output of the first EX-OR logic gate (EX2);
- a first transfer gate (T1, T2) which receives at the transfer input the output of said first inverter (I1), and which is controlled by input and output logic levels of said second inverter (I2);
- a second EX-OR logic gate (EX1) which receives input carry (Cin) and the output of said second inverter (I2) and supplies the addition result (S);
- and
- a first pair of series P-MOS transistors (T3, T4) and a second pair of series N-MOS transistors (T5, T6), said first and second pair being connected in series between two reference voltages, the bit of a first operand (A) being brought to the gate of a transistor of both pairs, the bit of a second operand (B) being brought to the gate of the other transistor of both pairs, the common node of said two pairs being connected to the output of said first transfer gate (T1, T2) and supplying the complemented output carry (CoutN),
- said cells being matrix-connected, at the input of each cell being present a NAND gate, the inputs of which receiving said two units of data X(i) and Y(j) of the corresponding position in the matrix, followed by a third inverter feeding one of the two operand inputs of the cell, the second input of each cell receiving the result output of the upstream cell receiving the result output of the upstream cell relevant to the propagation direction of the result, the carry input (Cin) of each cell receiving the output carry (Cout) of the upstream cell relevant to the carry signal path.
Dependencies are inferred from the claim text.