Digit-serial shifters constructed from basic cells

A shifter for digit-serial input signal having m-digit words supplied in successive n-bit digits, which successive digits are supplied in respective digit intervals and are consecutively ordinally numbered modulo m from first to zeroeth in each successive word, where m and n are each a respective positive integer greater than or equal to two, said shifter comprising:

• a control cell generating first and second control signals supplied via a first control signal bus and a second control signal bus respectively:
• first and second flip-flops of a synchronous SR type included in said control cell, each of said first and second flip-flops having a set input connection, a reset input connection, and true and not-true output connections which are complementary to each other, each of said first and second flip-flops responding to a ONE signal applied to its set or reset connection during a current digit interval only after a new digit interval is reached, each of said first and second flip-flops responding to ONEs being applied to both its set and reset connections as if a ONE were applied only to its reset connection, one of the output connections of said first flip-flop supplying said first control signal to said first control signal bus and a complementary one of the output connections of said second flip-flop supplying said second control signal to said second control signal bus;
• means for applying a final-digit signal to the reset input connection of said first flip flop and to the set input connection of said first flip-flop, said final-digit signal being a ONE during the zeroeth digits of words of said digit-serial input signal and being a ZERO during all other digits of said digit-serial input signal;
• means for applying a reset signal to the reset input connection of said second flip-flop, said reset signal having a value of ONE during digits of said digit-serial input signal having a specified ordinal number modulo m, and said reset signal having a value of ZERO during the remaining digits of said digit-serial input signal;
• means for applying a set signal to the set input connection of said first flip-flop, said set signal having a value of ONE during the digits of said digit-serial input signal having an ordinal number modulo m one more than said specified ordinal number modulo m, and said set signal having a value of ZERO during the remaining digits of said digit-serial input signal;
• a plurality n in number of bit-slice cells consecutively ordinally numbered from first through nth, having respective input signal bit connections receptive of bits of said digit serial input signal with significance increasing with increase in the ordinal number of the bit-slice cell, having respective output signal bit connections, and sharing a broadcast bit bus;
• a respective multiplexer included in each of said n bit-slice cells, having a respective first input connection to the input signal bit connection of the bit-slice cell that multiplexer is included in, having a respective second input connection to said broadcast bit bus, and having a respective output connection selecting a bit from said broadcast bit bus or from said input signal bit connection of the bit-slice cell in accordance with one of said first and second control signals supplied via its respective bus;
• at least one respective clocked unit-delay element included in each of said n bit-slice cells between the output connection of the multiplexer in that bit-slice cell and the output signal bit connection of that bit-slice cell, and arranged for being clocked at digit rate for said digit-serial input signal;
• and
• means for applying a broadcast bit signal to said broadcast bit bus.