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US 4,905,145 AGranted
Multiprocessor
AssigneeTexas Instruments Incorporated
InventorWilliam F. Sauber
Life of this patent
Estimating the term…
Abstract
A multiprocessor which includes a plurality of processing units interconnected by a global bus. Each processing unit has the capability for initiating control instructions including notification instructions and for selectively transmitting the control instructions over the global bus to the plurality of processing units and trigger device for initiating execution of the control instructions as a destination processing unit. A multiprocessor so constructed is capable of executing blocks of instructions sequentially or concurrently or both at required by a single program to reduce program execution time to a minimum.
Claims34
A multiprocessor comprising:
- (a) a plurality of processor systems, each processor system comprising memory means for storage of instructions and data, processor means for processing data responsive to predetermined instructions and memory interface means coupled to said memory means and said processor means for interfacing said memory means and said processor means,
- (b) a global bus interconnecting said memory interface means of each of said processor systems,
- (c) each said processor means including means to provide first instruction data including an address to its associated memory interface means,
- (d) each said memory interface means including means responsive to said first address signal from its associated processor means and non-coincidence of said first address signal in its associated memory to provide a second instruction data including an address signal on said global bus, and
- (e) means at each said memory interface means other than the memory interface providing said second instruction data including an address signal and responsive to said second instruction data signal to provide operation of its associated processor means and memory means in accordance with and responsive to said instruction data signal on said global bus.
2 more elements
A multiprocessor process, comprising the steps of:
- (a) providing a plurality of processor systems, each processor system comprising memory means for storage of instructions and data, processor means for processing data responsive to predetermined instructions and memory interface means coupled to said memory means and said processor means,
- (b) providing a global bus interconnecting said memory interface means of each said processor system,
- (c) providing first instruction data including an address signal at one of said processor means and sending said first instruction data including an address signal to memory interface means associated with said one processor means,
- (d) providing a second instruction data including an address signal from said memory interface means associated with said one processor means to said global bus responsive to said first instruction data including an address signal from said associated processor means and a non-coincidence of said first address signal in said associated memory bus, and
- (e) providing operation of said associated processor means and memory means of a second of said processor systems responsive to said second instruction data including an address signal on said global bus from said memory interface means associated with said one processor means in accordance with and responsive to said instruction data signal on said global bus.
2 more elements
A multiprocessor process comprising the steps of:
- (a) providing a plurality of processor systems, each processor system comprising memory interface means coupled to memory means for storage of instructions and data and processor means for processing data responsive to predetermined instructions and a global bus interconnecting each of said memory interface means,
- (b) providing an instruction data including address signal from a predetermined one of said processor means to its associated memory interface means,
- (c) determining the contents of the memory means associated with said memory interface means in response to said instruction data including address signal to obtain processing in said processing system in response to a non-coincidence of said first address signal,
- (d) providing an instruction data including address signal on said global bus in response to non-coincidence of said first address signal in said memory means in step (c), and
- (e) operating on said instruction data at a second of said processor systems in response to said instruction data.
2 more elements
A multiprocessor comprising:
- (a) a plurality of processor systems, each processor system comprising memory means for storage of instructions and data, processor means for processing data responsive to predetermined instructions and memory interface means coupled to said memory means and said processor means for interfacing said memory means and said processor means,
- (b) a global bus interconnecting said memory interface means of each of said processor systems,
- (c) each said processor means including means to provide first instruction data including a first notify signal to its associated memory interface means,
- (d) each said memory interface means including means responsive to said first notify signal from its associated processor means and non-coincidence of said notify signal in its associated memory to provide second instruction data including a second notify signal on said global bus, and
- (e) means at each said memory interface means other than the memory interface providing said second instruction data including a second notify signal and responsive to said second notify signal to provide operation of its associated processor means and memory means in accordance with and responsive to said instruction data on said global bus.
2 more elements
A multiprocessor process, comprising the steps of:
- (a) providing a plurality of processor systems, each processor system comprising memory means for storage of instructions and data, processor means for processing data responsive to predetermined instructions and memory interface means coupled to said memory means and said processor means,
- (b) providing a global bus interconnecting said memory interface means of each said processor system,
- (c) providing first instruction data including a notify signal at one of said processor means and sending said first instruction data including a notify signal to its associated memory interface means,
- (d) providing second instruction data including a notify signal from said associated memory interface means to said global bus responsive to said first instruction data including a notify signal from its associated processor means and a non-coincidence of said first notify signal in said associated memory bus, and
- (e) providing operation of said associated processor means and memory means responsive to a second notify signal on said global bus from a non-associated memory interface means in accordance with and responsive to instructions on said global bus.
2 more elements
A multiprocessor process comprising the steps of:
- (a) providing a plurality of processor systems, each processor system comprising memory interface means coupled to memory means for storage of instructions and data and processor means for processing data responsive to predetermined instructions and a global bus interconnecting said memory interface means,
- (b) providing instruction data including a first notify signal from a predetermined one of said processor means to its associated memory interface means,
- (c) determining the contents of the memory means associated with said memory interface means in response to said instruction data including said first notify signal to obtain processing in said processing system in response to a first predetermined condition,
- (d) providing a second instruction data including a second notify signal on said global bus in response to a second predetermined condition in step (c), and
- (e) operating on said instruction data at a second of said processor systems in response to said instruction data.
2 more elements
Dependencies are inferred from the claim text.