A control method of an array processor which receives a first vector data series C={c.sub.i }(i=1, 2, . . . , I) consisting of I first input vector data and a second vector data series R={r.sub.j }(j=1, 2, . . . , N) consisting of N second input vector data, and outputs a result of a predetermined computation, said control method comprising the steps of:
- using an array processor having n processing elements which are connected in the form of a ring via multiplexers and into which said first input vector data and said second input vector data are inputted;
- dividing said first input vector data into P groups (P is an integer equal to or larger than 1) by every n partial input vector data;
- executing a predetermined processing between said n partial input vector data of each group and said second input vector data;
- and
- repeating sequentially said predetermined processing between each of said P groups and said second vector data series to produce a final processing result from said processing elements;
- only one of said multiplexers transferring said first input data c.sub.i ;
- and at the same time the remaining multiplexers transferring respective outputs from preceding adjacent processing elements to the present processing elements;
- and
- said predetermined processing comprising the steps of:
- inputting a series of said n first input vector data c.sub.i into each of said processing elements via only one of said multiplexers in a pipelined fashion so that one of said processing elements receives said first input vector data c.sub.i through the multiplexer which selects the input data bus and the others receive the input vector data c.sub.i from the preceding adjacent processing elements;
- transferring circularly once inputted, said n first input vector data c.sub.i successively among the processing elements via all said multiplexers which select the data transfer path between the respective processing elements;
- inputting each successive one of said partial input vector data of each group directly into each one of said processing elements in synchronism with the cyclical data transfer of said n first input vector data c.sub.i in a pipelined fashion so that preceding partial input vector data c.sub.i which are transferred cyclically among said processing elements are replaced by the successive partial input vector data c.sub.i, or inputting each one of said second input vector data r.sub.j from an I/O data bus directly into each one of said processing elements in the sequence of said processing elements at every time and in synchronism with a timing that said partial input vector data c.sub.i is transferred cyclically among said processing elements or inputted into said processing elements;
- repeatedly inputting said partial input vector data c.sub.i in a pipelined fashion and cyclical data transfer of said input vector data c.sub.i, inputting said second vector data r.sub.j in synchronism with the partial vector data c.sub.i input or transfer, and transferring processing results between adjacent processing elements via said multiplexer which selects the data transfer path between adjacent processing elements;
- and
- simultaneously transferring processing parallel processed result data, which are obtained in each said processing elements among said processing elements ##STR6## times in parallel with the inner processing of said processing elements when the time unit is defined as the processing between each one of said n first input vector data c.sub.i and each one of said second input data r.sub.j, in case that processing results in one group of n first input vector data c.sub.i and said second input vector data r.sub.j are used for the processing of the following group of n first vector data c.sub.i and said second input vector data r.sub.j, with ##STR7## being the division remainder of the division of N by n.