Floating gate memories
AssigneeAmerican Telephone and Telegraph Company, AT&T Bell Laboratories
InventorsFabio Beltram, Federico Capasso, Roger J. Malik, Nitin J. Shah
Life of this patent
Estimating the term…
Abstract
A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.
Claims10
A memory device comprising
- source, drain and control gate electrode means,
- a semiconductor channel for conducting carriers from said source to said drain means, characterized by
- a semiconductor heterostructure disposed between said channel and control gate means, said heterostructure including a floating gate potential well for confining carriers in a region sufficiently close to said channel to at least partially deplete it and further including a graded bandgap injector region for controlling the flow of carriers between said control gate means and said potential well.
Dependencies are inferred from the claim text.