US 4,904,958 A · Enhanced phase detector

Abstract

An enhancement for a phase locked loop, where the enhanced phase locked loop includes a phase detector having an output and first and second inputs, the enhancement circuits of the invention, a loop filter and a voltage controlled oscillator having a control signal input and a signal output connected to the second input of the phase detector. One embodiment of the enhancement comprises a first amplifier for amplifying the output signal from the phase detector, a matched quad diode array having first and second nodes, a second amplifier and first, second and third resistors each having first and second terminals. The first terminal of the first resistor is connected to the first terminal of the third resistor and also connected in common to the first amplifier output. The second terminal of the third resistor is connected to the second node of the quad diode array, the first terminals of the first and third resistors and the inverting input of the second amplifier. The second amplifier's output is connected to the second terminal of the second resistor and further connected to the loop filter input. The loop fitler is, in turn, connected to the control signal input to complete the circuit for the enhanced phase locked loop. In operation, the control signal responds to variations in forward conductivity of the matched diode array which, in turn, responds to the voltage swings of the amplified phase detector output.

Claims6

Dependent claims

A phase locked loop comprising:

(a) a phase detector having first and second inputs and an output;
(b) a first means for amplifying the phase detector output;
(c) a means for generating a voltage controlled oscillation signal to the first input, where the voltage controlled oscillation means includes a voltage control signal input;
and
(d) means for providing a control signal to the voltage control signal input wherein the means for providing a control signal further comprises first, second and third resistance means, an array of diodes, a second amplifying means and a capacitance means having first and second plates, wherein the diode array has first and second nodes and the first node is connected to one terminal of the third resistance means and the second node is connected to the inverting input of the second amplifying means and, wherein a first terminal of the first resistance means is connected to the second terminal of the third resistance means and also in common to the amplified phase detector output, further, wherein the second terminal of the first resistance means is connected to a first terminal of the second resistance means and also in common to the inverting input of the second amplifying means, further, wherein a second terminal of the second resistance means is connected to a first plate of the capacitance means and a second plate of the capacitance means is connected to the output of the second amplifying means, and wherein the control signal is responsive to the amplified phase detector output such that varying forward conduction of the amplified phase detector output increases the amplitude of the control signal when forward conduction is increased.

2 more elements

A phase locked loop comprising:

(a) a phase detector having first and second inputs and an output;
(b) a first means for amplifying the phase detector output;
(c) a means for generating a voltage controlled oscillation signal to the first input, where the voltage controlled oscillation means includes a voltage control signal input;
and
(d) means for providing a control signal to the voltage control signal input wherein the means for providing a control signal further comprises first, second, third, fourth and fifth resistance means, a capacitance means, an array of diodes, a second amplifying means and a third amplifying means wherein the diode array has first and second nodes and the first node is connected to one terminal of the third resistance means and the second node is connected to the inverting input of the second amplifying means, and, wherein a first terminal of the first resistance means is connected to the second terminal of the third resistance means and also in common to the amplified phase detector output, further, wherein the second terminal of the first resistance means is connected to a first terminal of the second resistance means and also in common to the inverting input of the second amplifying means, a second terminal of the second resistance means is connected to the output of the second amplifying means, the fourth resistance means has a first terminal connected to the output of the second amplifying means and a second terminal connected to a first terminal of the fifth resistance means and in common with the inverting input of the third amplifier means, and wherein the fifth resistance means has a second terminal connected to one side of the capacitance means, the capacitance means further has the other side connected to the output of the third amplifier means, and wherein the control signal is responsive to the amplified phase detector output such that varying forward conduction of the amplified phase detector output increases the amplitude of the control signal when forward conduction is increased.

2 more elements

Dependencies are inferred from the claim text.

Enhanced phase detector

Life of this patent

Enhanced phase detector

Life of this patent

Abstract

Claims6