Output circuit for outputting a level shifted output signal
AssigneeKabushiki Kaisha Toshiba
InventorMasaji Ueno
Life of this patent
Estimating the term…
Abstract
An output circuit provides a high voltage output signal in response to a low voltage input signal. The output circuit includes a pull-up transistor for raising the output signal substantially to a power source voltage level and a pull-down transistor responsive to the input signal for lowering the output signal substantially to the ground level. The pull-up transistor is biased by a self-bias circuit triggered by a prescribed level of a control signal. The self-bias circuit continues to bias the pull-up MOS transistor in order to bring the output signal level to the high voltage level, even if the prescribed level period of the control signal terminates.
Claims12
An output circuit responsive to an input signal having a first voltage level for a prescribed period and a second voltage level for a specified period, a reference voltage and a power source voltage, comprising:
- control signal generating means responsive to the input signal for outputting a control signal having a predetermined voltage level for a short period less than the prescribed period following the prescribed period of the input signal;
- self-bias circuit means for producing a bias voltage established in a self-bias manner and triggered by the control signal;
- pull-up circuit means biased by the bias voltage of the self-bias circuit means for raising the voltage level of the output signal substantially to the level of the power source voltage;
- and
- pull-down circuit means responsive to the first voltage level of the input signal for lowering the voltage level of the output signal substantially to the level of the reference voltage.
An output circuit for outputting a high voltage output signal in response to a power source voltage, a reference voltage and a low voltage input signal having a first voltage level for a prescribed period and a second voltage level for a specified period, for discharging a capacitance connected to an output terminal during the prescribed period and for charging the capacitance during the specified period, comprising:
- control signal generating means responsive to the input signal for outputting a control signal having a predetermined voltage level for a predetermined period shorter than the specified period of the input signal and following the prescribed period of the input signal;
- pull-up circuit means for supplying a predetermined current to the output terminal to charge the capacitance;
- self-bias circuit means for biasing the pull-up circuit means by supplying a predetermined bias voltage established in a self-bias manner and triggered by the control signal and
- pull-down circuit means responsive to the input signal for discharging the capacitance.
Dependencies are inferred from the claim text.