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US 4,904,887 AGranted
Semiconductor integrated circuit apparatus
AssigneeFujitsu Limited
InventorsEiji Sugiyama, Mitsuaki Natsume, Toshiharu Saito
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated-circuit apparatus includes an electro-conductive layer formed on a substrate, a plurality of internal cells formed on the electro-conductive layer, a plurality of bonding pads arranged around the internal cells, and a plurality of bias cells which are common to the plurality of internal cells and which generate a predetermined voltage. A plurality of bias buffer circuits supply the predetermined voltage generated in the bias cells to the internal cells.
Claims10
A semiconductor integrated circuit apparatus having a substrate, comprising:
- a first voltage source;
- a second voltage source having a lower voltage than said first voltage source;
- a plurality of internal cells formed on a center portion of the substrate, said plurality of internal cells divided into a plurality of groups of internal cells, each of said internal cells including:
- a plurality of gate circuits each including:
- a pair of first transistors having emitters commonly connected, having collectors operatively connected to said first voltage source, and having bases;
- and
- a second transistor having a collector operatively connected to said commonly connected emitters of said first transistor, having an emitter operatively connected to said second voltage source, and having a base;
- a bias buffer circuit operatively connected to said plurality of gate circuits;
- an electro-conductive layer formed on the substrate and said plurality of internal cells;
- a plurality of bonding pads, formed so as to operatively connect said electro-conductive layer, arranged about the periphery of said plurality of internal cells;
- and
- a plurality of bias cells, operatively connected to said respective groups of said plurality of internal cells, each of said plurality of bias cells providing a first predetermined constant voltage to each of said bias buffer circuits in each of said plurality of groups of internal cells and each of said bias buffer circuits providing second and third predetermined constant voltages to respective bases of one of said first transistors and the second transistor of said plurality of gate circuits in said respective internal cells, the number of said bias cells being smaller than the number of said bias buffer circuits.
9 more elements
A semiconductor integrated circuit apparatus having a substrate, comprising:
- a first voltage source;
- a second voltage source having a lower voltage than said first voltage source;
- a plurality of internal cells formed on a center portion of the substrate, said plurality of internal cells divided into a plurality of groups of internal cells each of said internal cells including:
- a plurality of gate circuits each including:
- a pair of first transistors having commonly coupled emitters, having collectors operatively connected to said first voltage source, and having bases;
- and
- a second transistor having a collector operatively connected to said commonly coupled emitters of said first transistors, having an emitter operatively connected to said second voltage source, and having a base;
- and
- a bias buffer circuit operatively connected to said plurality of gate circuits and operatively connected between said first and second voltage sources;
- an electro-conductive layer formed on the substrate and said plurality of internal cells;
- a plurality of bonding pads, operatively connected to said electro-conductive layer, arranged about the periphery of said plurality of internal cells;
- and
- a plurality of bias cells operatively connected to said respective groups of said plurality of internal cells, each of said plurality of bias cells providing a first predetermined constant voltage, which is higher than the second voltage source by a predetermined level, to each of said bias buffer circuits in each of said plurality of groups of internal cells, each of said bias buffer circuits providing a second predetermined constant voltage and a third predetermined constant voltage, which is lower than said second predetermined constant voltage, to said respective bases of one of said first transistors and said second transistor of said plurality of gate circuits in said respective internal cells.
10 more elements
Dependencies are inferred from the claim text.