US 4,904,613 AGranted

Method of manufacturing a DMOS device

AssigneeU.S. Philips Corporation

InventorsDavid J. Coe, Kenneth Whight, Richard J. Tree

Life of this patent

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Abstract

A method of manufacturing a semiconductor device in which a conductive layer (6) provided on a surface (4) of a semiconductor body (1) is formed with at least one opening (10). The semiconductor device may be an insulated gate field effect transistor (IGFET) in which case the opening (10) defines a hollow gate structure for the IGFET. Insulating material (16') is grown on the surface (4) to cover the conductive layer. The opening or openings (10) are sufficiently small and the growth of insulating material is continued for a sufficiently long period that insulating material growing on edges (8"a) of the conductive layer bounding the openings (10) meets to close the openings so that subsequent etching of the insulating material anisotropically towards the surface (4) to expose a surface of the conductive layer and/or to form a window (18) within insulating material covering an area of the semiconductor body surface larger than the openings and not covered by the conductive layer, leaves insulating material (19,17) on edges of the conductive layer so that the openings remain closed. Where the semiconductor device is an IGFET impurities to form the source and channel regions may be introduced via the window.

Claims8

Dependent claims

A method of manufacturing gas field effect transistor comprising the steps of:

(a) forming an insulating layer on a surface of a semiconductor body,
(b) forming at least one insulated gate structure on said insulating layer by providing separated conductive gate regions on said insulating layer,
(c) forming an opening through each of said conductive gate regions to said insulating layer, said opening being smaller than separation of said separated conductive gate regions,
(d) growing insulating material on said separated conductive gate regions for a period sufficient to close said opening through each of said conductive gate regions, said insulating material also being grown on said insulating layer between said separated conductive gate regions,
(e) anisotropically etching said insulating material toward said surface of said semiconductor body until said surface is exposed between said separated conductive gate regions, but insulating material remains on edges of said conductive gate regions and said openings remain closed, said insulating material remaining on said edges forming at least in part at least one window through said insulating material to said surface.
(f) introducing impurities through said at least one window to form source regions registered with said insulated gate regions, said source regions being of one conductivity type, and to form channel regions of an opposite conductivity type beneath said insulated gate regions.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/135,880Filed 21 Dec 1987
Priority: GB 863081423 Dec 1986
Granted: 27 Feb 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/66
Double-diffused metal-oxide semiconductor [DMOS] FETs: vertical dmos [vdmos] fets
H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 64/252
Source or drain electrodes for field-effect devices: for vertical or pseudo-vertical devices
H10D 64/2527
For vertical or pseudo-vertical devices: for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies