Wafer level process for fabricating passivated semiconductor devices

A process for fabricating a multiplicity of semiconductor devices, said process comprising the steps of:

• applying electrodes to both faces of a semiconductor wafer;
• mounting said semiconductor wafer on a substrate by means of an intervening layer of adhesive which bonds to the substrate and to the wafer;
• dividing the wafer while mounted into a multiplicity of chips by forming grooves which extend through the wafer and partly through said layer of adhesive without extending into said substrate;
• putting a resin into said grooves which passivates sidewalls of the chips, bonds to the sidewalls of said chips and interconnects said chips;
• curing said resin;
• separating said cured resin and chips from said substrate, whereby said chips and cured resin form a discrete unit separate from said substrate;
• after the separating step, applying heated, melted solder to said chips and bonding substance while in said discrete unit at such a temperature that said cured resin withstands the heat of said solder;
• and
• after the solder is applied, dividing said discrete unit with applied solder into cells, each cell including one of said chips and applied portion of the solder.