Phase determining circuit to generate a phase control signal, and method for generating said signal

A method of determining, by digital data processing, the phase of a reference phase pulse signal (1') with respect to an actual phase pulse signal (2') and deriving a control output signal (10) in dependence on the relative temporal position of said phase pulse signals, said method comprising the steps of:

• counting, at a clock rate high with respect to the pulse repetition rate of the phase reference pulse signal, and providing counter numbers in dependence on the count number at the time of occurrence of the actual phase pulse signal (2'), and
• varying the counting clock rate in dependence on deviation of the counter number at which the actual phase pulse signal occurs from a predetermined desired count number by comparing the temporal occurrence of the actual pulse signal (2') within a window range of count numbers and controlling the rate of counting as a function of the extent of deviation of the count number contemporaneous with the actual phase pulse signal (2'), within said range, from said desired count number.

A method of determining, by digital data processing, the phase of a reference phase pulse signal (1') with respect to an actual phase pulse signal (2') and deriving a control output signal (10) in dependence on the relative temporal position of said phase pulse signals, said method comprising the steps of:

• counting, at a clock rate high with respect to the pulse repetition rate of the phase reference pulse signal, and providing count numbers in dependence on the count number present at the time of occurrence of the actual phase pulse signal (2');
• increasing said counting clock rate as the extent of deviation of the count number present at the time of the actual pulse signal (2') from a predetermined desired count number decreases, so that the slope of the counting rate increases as the temporal position of the actual pulse signal (2') with respect to the pulse reference signal (1') causes said desired number to be approached, for thereby reducing the time interval between succeeding count numbers, and
• decreasing said counting clock rate whenever said deviation extent exceeds a predetermined comparison window range for comparison of count numbers with said predetermined desired count number.