Circuit arrangement for serial data transmission between a plurality of subscriber stations

In a circuit arrangement for serial data transmission between first and second subscriber stations connected to respective first and second transmission/receiving devices and each of the subscriber station including a data transmitter and a data receiver, each data transmitter and each data receiver connected to two leads of a data bus, each of said transmitters including a control input responsive to control signals from the other transmitter such that only one of the transmitters is active at a time to output a voltage of a first polarity or of a second polarity dependent on the state of a data signal applied thereto by the respective transmission/receiving device, each of the transmitters having a higher internal impedance in the passive condition than in the active condition, and each of the receivers operable in response to the polarity of the voltage received from the other station to output data to the respective transmission/receiving device, the improvement therein comprising:

• a resistor arrangement connected to the data bus and connecting both leads thereof via resistors to the same potential;
• and
• a recognition circuit in at least one of the subscriber stations connected to the two leads of the data bus and responsive to at least approximately identical voltages on the leads of the data bus to output a free control signal having a first logic state and responsive to different voltages of the leads of the data bus to output a busy control signal having a second logic state.