Semiconductor memory device having on-chip error check and correction functions

A semiconductor memory device having on-chip error checking and correcting functions comprising:

• a plurality of memory cell arrays, said arrays including a data bit memory cell array for storing data words of m bits each and a check bit memory cell array for storing data including error correction codes having k check bits each;
• error checking and correcting means including
• (a) error code generation means for receiving input data words and, in response, generating said error correction codes,
• (b) error code writing means for storing said error codes in said check bit memory cell array, and
• (c) data correction means for reading said data words stored in said data bit memory cell array and said error codes stored in said check bit array and, in response thereto, supplying a corrected data word output;
• clock input means for receiving a switching control signal;
• means for disabling said on-chip error checking and correcting means in response to an external test mode enable control signal (TE);
• data writing means for writing data into said memory cell arrays;
• and
• data reading means for supplying data words from said data correction means and from said check bit memory cell array, said data reading means including a single data output terminal and switching mans responsive to said switching control signal for alternatingly accessing said check bit memory cell array and said data bit memory cell array through said error checking and correction means for successively outputting check bits and data bits from said single data output terminal in an interleaved manner.