US 4,903,266 A · Memory self-test

Abstract

A system and method for on-chip self test of memory circuits is disclosed. Memory circuit testing is accomplished by using a random pattern generator based upon a primitive polynomial and including a linear feedback shift register having at least one stage in addition to the number of address lines required for addressing the memory. The random pattern generator is capable of cycling through all memory addresses, including the all zero address. During each of four random pattern generator cycles, known data is written in or read out of each memory cell. By including means for writing and reading the complement of data during different random pattern generator cycles, both possible states of each memory cell may be tested. The outputted data is routed to multiple input signature register which generates a data signature for the memory which can in turn be compared to that known for a good memory. Logic circuit testing may also be accomplished using a known level sensitive scan design technique, the test output data also being outputted to the multiple input signature register. A single data signature may then be generated which is indicative of the good or bad status of both the logic and memory circuits.

Claims10

Dependent claims

A method for self-test of logic circuits and memory circuits having a random pattern generator connected to input lines of the logic circuits and address lines and data input lines of the memory circuits, the random pattern generator including means for stepping through each memory address during a random pattern generator cycle, the logic and memory circuits having a multiple input signature register connected to output lines thereof, comprising:

providing the random pattern generator with known seed data;
writing data into the memory circuits during a first random pattern generator cycle;
outputting data from the memory circuits to the multiple input signature register during a second random pattern generator cycle;
writing data into the memory circuits during a third random pattern generator cycle, the data written during the third random pattern generator cycle being the complement of the data written during the first random pattern generator cycle;
outputting data from the memory circuits to the multiple input signature register during a fourth random pattern generator cycle;
scanning data through the logic circuits and into the multiple input signature register;
and
comparing the data signature in the multiple input signature register with that which would be generated by properly operating logic and memory circuits provided with the same seed data.

5 more elements

Dependencies are inferred from the claim text.

Memory self-test

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Memory self-test

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Abstract

Claims10