Time-division multiplex switching network

A time-division switching network, comprising:

• a plurality of basic switches, each said basic switch constituting a stage of said switching network and respectively comprising:
• a plurality of input buses each of which is effective for transferring a first time-division multiplexed signal;
• a plurality of output buses, each of which is effective for transferring a second time-division multiplexed signal;
• a plurality of means for providing frame synchronization data to the time-division multiplexed signal on each of said plurality of input and output buses;
• and
• a plurality of time switches;
• each of said plurality of input buses being connected to each of said plurality of output buses by a respective one of said plurality of time switches;
• for receiving the first time-division multiplexed signal from a corresponding one of said input buses, and for outputting the second time-division multiplexed signal onto a corresponding one of said output buses;
• the output buses of the basic switch at each said stage being suitable for being connected, in one-to-one correspondence, to the input buses of another basic switch which forms a next stage in the switching network, said plurality of input buses of the basic switch at a first stage being connected to a plurality of input means, and said plurality of output buses of the basic switch at a last stage being connected to a plurality of output means;
• wherein each of said time switches includes:
• a data memory having a write data input terminal which is connected to the input bus and a read data output terminal which is connected to the output bus;
• data-writing means connected to the input bus for detecting a frame phase of the input bus in accordance with the frame synchronization signal provided to the time-division multiplexed signal on the input bus, for aligning the detected frame phase with a frame phase of first control data, and for writing a data signal from the input bus at an address of said data memory indicated by the first control data;
• and
• data-read-out means connected to the output bus for detecting a frame phase of the output bus in accordance with the frame synchronization signal provided to the time-division multiplexed signal on the output bus, for aligning the detected frame phase with a frame phase of second control data, for reading out the data signal from an address of said data memory indicated by the second control data and for outputting the readout data onto the output bus.

A time switch, comprising:

• a plurality of input buses;
• a plurality of output buses;
• a memory consisting of a plurality of areas respectively assigned to said input buses;
• each area having a memory input and a memory output;
• means for producing a first control signal on a first control output;
• means for producing respective second control signals on respective second control outputs;
• a plurality of write means with respective data inputs respectively connected to the input buses, with outputs respectively connected to memory inputs and with respective control inputs connected to said first control output, for writing in said memory data signals associated with said input buses via said memory inputs in accordance with said first control signal;
• and
• a plurality of read means with respective data outputs respectively connected to the output buses, with inputs respectively connected to memory outputs and with respective control inputs respectively connected to said respective second control outputs, for reading out from said memory the data signals via said memory outputs in accordance with said second control signal.