Semiconductor memory having a parallel input/output circuit

A memory circuit comprising a memory array having a plurality of word lines arranged in rows including first and second outermost rows, a plurality of digit lines arranged in columns normal to said rows, and a plurality of memory cells arranged in an array and coupled to said word plurality lines and said digit lines, each of said memory cells being coupled to only one of said word lines and including data storage means having a data node and a transfer gate having a controllable current path connected between said data node and one of said digit line and a control electrode connected to the one of said word lines to which the memory cell is connected, a row decoder coupled to said word lines for operatively selecting one of said word lines in response to row address information thereby to enable the transfer gates of the memory cells coupled to the selected word line, a column selection circuit coupled to said digit lines for operatively selecting a number of said digit lines in response to column address information for data access thereto, a number of signal lines, a parallel read-write unit coupled to said number of signal lines and to a number of memory cells in the first outermost row of said memory array corresponding to the number of signal lines, said parallel read-write unit including read-write circuits of a corresponding to the number of signal lines, each of said read-write circuits having a first node coupled to one of said signal lines and a second node directly connected to the data node of one of said cells in said first outermost row coupled to said parallel read-write unit, each of said read-write circuits transferring a signal at the first node thereof to the second node thereof in a first mode and transferring a signal at said second node to said first node in a second mode, first control means coupled to said read-write circuits for simultaneously setting said read-write circuits in said first mode thereby to simultaneously write signals on said signal lines into the storage means of said memory cells in said first outermost row coupled to said parallel read-write unit, and second control means coupled to said read-write circuits for simultaneously setting said read-write circuits in said second mode thereby to simultaneously read out to said signal lines the states of the storage means of said memory cells in said first outermost row coupled to said parallel read-write unit.