Semiconductor memory device with improved immunity to supply voltage fluctuations
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHideshi Miyatake, Masaki Kumanoya, Katsumi Dosaka
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Abstract
A semiconductor memory device such as a static RAM (Random Access Memory) device comprises a ground connection circuit of n channel field effect transistors connected between two I/O lines and the ground. The precharge circuit for precharging and the ground connection circuit both operate in response to the signal which is in synchronization with an externally applied external chip select signal. Therefore, the access delay derived from the fluctuation of the supply voltage generated before the change of the external chip select signal can be prevented.
Claims17
A semiconductor memory device comprising:
- first and second I/O bus lines;
- precharge means connected to a source of a first voltage potential and said first and second I/O bus lines for precharging said first and second I/O bus lines in response to a variable state signal;
- equalizing signal generation means for generating an equalizing signal in response to a clock signal;
- equalizing means connected between said first and second I/O bus lines for establishing an equipotential of said first and second I/O bus lines in response to said equalizing signal;
- and
- ground connection means connected to said first and second I/O bus lines for supplying a source of ground potential thereby bringing said first and second I/O bus lines to said ground level potential in response to said variable state control signal.
A static random access memory device comprising
- a power supply;
- ground;
- first and second I/O bus lines;
- precharge circuit connected between said power supply and said first and second I/O bus lines for precharging said first and second I/O bus lines in response to an externally applied external chip select signal;
- equalize signal generation circuit for generating an equalizing signal in response to a clock signal;
- equalizing circuit connected between said first and second I/O bus lines for equalizing said first and second I/O bus lines in response to said equalizing signal;
- and
- ground connection circuit connected between said first and second I/O bus lines and said ground for bringing said first and second I/O bus lines to the voltage of the ground level in response to said external chip select signal.
In a semiconductor memory including first and second I/O bus lines, a method for accessing a semiconductor memory device to minimize delays caused by supply voltage fluctuations comprising the steps of:
- detecting a first state of a chip select signal;
- applying a source of ground potential to said first and second I/O bus lines in response to detecting said first state of said chip select signal;
- detecting a second state of said chip select signal;
- applying a precharge voltage potential to said first and second I/O bus lines in response to detecting said second state of said chip select signal;
- generating an equalizing signal in response to a clock signal;
- establishing an electrical connection between said first and second I/O bus lines in response to said equalizing signal to create an equipotential of said bus lines.
Dependencies are inferred from the claim text.