Nonvolatile semiconductor memory device and a writing method therefor
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakeshi Nakayama, Kazuo Kobayashi, Yasushi Terada
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Abstract
In an erase mode, a high DC voltage Vpp is applied to all of the word lines and zero volt is applied to all of the bit lines, whereby the contents of all of the memory transistors are simultaneously erased. In a write mode, which constitutes an essential feature of the present invention, zero volt is applied to a selected word line and the high DC voltage Vpp is applied to a selected bit line, with an intermediate voltage 1/2.Vpp being applied to the other word lines and bit lines. Thus, by electron tunneling, data is written in a memory transistor located at a point of intersection between the selected word line and the selected bit line.
Claims18
A nonvolatile semiconductor memory device formed on one chip of a semiconductor substrate in an integrated manner, said device having a plurality of word lines, a plurality of bit lines intersecting with said word lines, and a plurality of memory cells, each said memory cell being a single transistor-type cell provided at an intersection of said plurality of word lines and said plurality of bit lines for storing information in a nonvolatile manner, comprising:
- an internal DC power supply provided on said semiconductor substrate,
- means for generating a high DC voltage for writing data into said memory cells and erasing the data written into said memory cells,
- said means for generating the high DC voltage comprising first voltage increasing means for increasing an output voltage of said internal DC power supply,
- means for generating an intermediate voltage higher than a ground voltage and lower than said high DC voltage,
- said means for generating the intermediate voltage comprising second voltage increasing means for increasing an output voltage of said internal DC power supply,
- addressing means for selecting a word line and a bit line intersecting at a selected memory cell,
- word line voltage applying means for applying said high DC voltage and one of said intermediate voltage and said ground voltage to said word lines dependent on an operation cycle of said nonvolatile semiconductor memory device, and
- bit line voltage applying means for applying said high DC voltage and one of said intermediate voltage and said ground voltage to said bit lines dependent on the operation cycle of said nonvolatile semiconductor memory device,
- said word line voltage applying means including word line write voltage applying means for applying said ground voltage to the word line selected by said addressing means and applying said intermediate voltage to the non-selected word lines in a write cycle of data into said memory cells,
- said bit line voltage applying means including bit line write voltage applying means for applying said high DC voltage to the bit line selected by said addressing means and applying said intermediate voltage to the non-selected bit lines in said write cycle.
A method for writing data in a nonvolatile semiconductor memory device having a plurality of word lines, a plurality of bit lines intersecting with said word lines, and a plurality of memory cells, each said memory cell being a single transistor-type cell provided at an intersection of said plurality of word lines and said plurality of bit lines for storing information in a nonvolatile manner, said memory device further having a single source line connected to a corresponding terminal of each of said memory cells, comprising:
- for writing,
- selecting a word line and a bit line intersecting with a selected memory cell,
- applying a ground voltage to said selected word line,
- applying a high DC voltage to said selected bit line, and
- applying an intermediate voltage to non-selected word lines and bit lines, said intermediate voltage being higher than said ground voltage and lower than said high DC voltage, and
- leaving floating said source line connected to each of said memory cells.
A non-volatile semiconductor memory device comprising:
- a plurality of memory cells arranged in rows and columns of a matrix, each of said memory cells having a first main electrode region of a second conductivity type on a semiconductor substrate of a first conductivity type, a second main electrode region of the second conductivity type formed on the surface of said substrate and between the surface and said first main electrode region and separated therefrom by first and second channel regions, a floating gate having a first portion formed on said first channel region of the substrate and separated therefrom by a first insulating film and a second portion formed on said first main electrode region and separated therefrom by a second insulating film thinner than the first insulating film, and a controlling gate having a first portion formed on said second channel region of the substrate and separated therefrom by a third insulating film and a second portion formed on said floating gate and separated therefrom by a fourth insulating film,
- a plurality of word lines, each connected to each of the control gates of the memory cells arranged in each row,
- first means for applying a first potential to all the word lines at a time of erasing, for applying a second potential to the word lines connected to selected memory cells and for applying a fourth potential intermediate between the second potential and a third potential to the remaining word lines at a time of writing,
- a plurality of bit lines, each connected to each of said first main electrode regions of the memory cells arranged in each column, and second means for applying a fifth potential to all the bit lines at the time of erasing, said first means for applying operable for applying said third potential to the bit lines connected to the selected memory cells and applying said fourth potential to the remaining bit lines at the time of writing,
- a plurality of lines for said second main electrode, each connected to said second main electrode regions of each of the memory cells arranged in each column, all of the lines for the second main electrode regions being made electrically floating.
A memory cell of a non-volatile semiconductor memory device comprising:
- a first main electrode region of a second conductivity type, connected to a corresponding bit line, formed on a surface of a substrate of a first conductivity type, a second main electrode region of the second conductivity type formed on the surface of said substrate and separated from said first main electrode region by first and second channel regions,
- a floating gate having a first portion formed on said first channel region of the substrate and separated therefrom by a first insulating film and a second portion formed on said first main electrode region and separated therefrom by a second insulating film thinner than the first insulating film, said second portion of said floating gate having a depressed region, and
- a control gate having a first portion formed on said second channel region of the substrate and separated therefrom by a third insulating film and a second portion formed on said floating gate and separated therefrom by a fourth insulating film, said control gate having a projecting region opposite said depressed region of said second portion of said floating gate, said control gate being connected to the corresponding word line.
Dependencies are inferred from the claim text.