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US 4,903,235 AGranted
Semiconductor memory
AssigneeHitachi, Ltd.
InventorsTaei Kubota, Tetsuo Nakano
Life of this patent
Estimating the term…
Abstract
A semiconductor memory includes an array of memory cells wherein each memory cell is disposed at the intersection between a word line and a data line. An output line of the memory is coupled to the data line via transfer MOSFET and a data line signal detecting circuit, the latter being provided between the common data line and the output line. A precharging circuit for precharging the data line and a feedback circuit for coupling together the output and input sides of the data line signal detecting circuit are provided.
Claims5
A semiconductor memory comprising:
- a word line;
- a plurality of data lines;
- a plurality of memory cells each of which is disposed at an intersection between said word line and one of said data lines;
- a common data line;
- a plurality of first MOSFETs each of which has a first conductivity type and is coupled between one of said data lines and said common data line;
- selecting means coupled to said first MOSFETs and including means for controlling the operation of each of said first MOSFETs;
- amplifier means coupled to said common data line and including means for providing an output signal having an inverted level with respect to an signal on said common data line;
- and
- a second MOSFET having a second conductivity type, coupled to said common data line and responsive to said output signal for providing a predetermined voltage level to said common data line.
6 more elements
A semiconductor memory comprising:
- a word line;
- a plurality of data lines;
- a reference line;
- a plurality of memory cells each of which is disposed at an intersection between said word line and one of said data lines, wherein at least one memory cell includes a first MOSFET having a gate electrode coupled to said word line, a first electrode coupled to a corresponding data line and a second electrode coupled to said reference line;
- a common data line;
- a plurality of second MOSFETs each of which has a first conductivity type and is coupled between each of said data lines and said common data line;
- selecting means coupled to said second MOSFETs and including means for controlling the operation of each of said second MOSFETs;
- amplifier means coupled to said common data line and including means for providing an output signal which has an inverted level with respect to a signal on said common data line;
- and
- a third MOSFET having a second conductivity type, coupled to said common data line and responsive to said output signal for providing a predetermined voltage level to said common data line.
7 more elements
Dependencies are inferred from the claim text.