US 4,903,231 AGranted

Transposition memory for a data processing circuit

AssigneeSGS-Thomson Microelectronics S.A.

InventorAlain Artieri

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Abstract

A memory of n.times.n digital data, is adapted to receive the n.times.n data from a matrix block in line order after line and to output the data in column after column order. Such a memory is particularly useful for circuits carrying out digital transformations such as cosinus transformations wherein one must first carry out a line transformation then a column summation. The memory is constituted by a network of n.times.n registers REG(i,j) and of n.times.n multiplexers MUX(i,j); the registers are operated at a period T and the multiplexers at a period n.times.T. The connections between the memory inputs and outputs and the register network are alternatively connected at the period n.times.T in order that in a first phase the data are introduced and "horizontally" shifted inside the network and that in a second phase the data are introduced and "vertically" shifted.

Claims4

Dependent claims

A transposition memory comprising n inputs (E0 to En-1) for receiving n.times.n data groups line after line, and n outputs (S0 to Sn-1) for outputting the data grouped according to successive columns, the data being the n.times.n data of a data square matrix, the data being further transmitted and processed in the form of electrical signals, further comprising a network of n.times.n registers (REG(i,j)) and of n.times.n multiplexers (MUX(i,j)), arranged in lines and columns, each register being associated with one multiplexer and being marked by its location in line i and its location in column j, the multiplexer (MUX(i,j)) having a first input connected with the output of register REG(i,j-1), a second input connected with the output of register REG(i+1,j) and an output connected with the input of register (REG(i,j)), the multiplexer output transmitting the status of the first input during a first operating phase (a) of the memory and further transmitting the status of the second input during a second phase (b), and the connections of the registers and multiplexers of the first and last lines and columns of the network being as follows:

(a) the first inputs of the multiplexers of the first column (rank 0) are each connected with a respective input of the memory;
(b) the outputs of the registers of the last column (rank n-1) are each connected through a respective switch with a respective output of the memory, this switch being closed during the first phase and open during the second phase;
(c) the output of each register of the first line (rank 0) is connected, through a switch open during the first phase and closed during the second phase, with a respective output of the memory;
(d) the second input of each multiplexer of the last line (rank n-1) is connected with a respective input of the memory.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 07/214,252Filed 1 Jul 1988
Priority: FR 87/094583 Jul 1987
Granted: 20 Feb 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 7/78
Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data: for changing…
G06F 17/16
Complex mathematical operations: matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
G06F
Computing and data processing