Single cycle merge/logic unit

A data processing circuit for performing either a merge or Boolean logic operation on data within a single clock cycle in response to an instruction, said circuit comprising:

• control means for receiving an instruction during a clock cycle and providing a selection signal, a rotator signal and a control signal to specify either a merge or a Boolean logic operation in response to said instruction;
• data selector means for providing a plurality of data words, each containing a plurality of bits, in response to the selection signal;
• rotator means connected to said data selector means for rotating the bits of at least one of said provided data words in response to the rotator signal;
• and
• logic means for logically combining the bits from said data words from said data selector means and said rotator means in response to the control signal and including means for performing a mask operation within said clock cycle upon a first word from said data selector means with a mask word provided by said data selector means