Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank

A memory bank selection arrangement for use in a data processing system including a memory which has a number of banks, wherein first bits of a memory address are used for addressing a location in a selected bank to read or write therein and are incrementable by an address controller before being used to address a bank of said memory, wherein said address controller generates a carry output when the incrementing of said first bits result in there being a carry from the highest order bit of said first bits, and said address includes second bits for identifying a bank in said memory to be selected and then addressed by the first bits, of said address, said arrangement comprising:

• a bank selector to which said second bits indicating said selected bank of memory are input, said bank selector being responsive to said carry output generated by said address controller to increment the binary number represented by said second bits, and the second bits, then being used to select a bank in said memory to be addressed using said first bits.

A method used in a data processing system for selecting a bank in a memory which has a number of banks, wherein first bits of an address used for addressing a location in a selected bank of said memory are incrementable before being used to address the memory, wherein a carry output is generated when the incrementing of said first bits results in there being a carry from the highest order bit of said first bits, and said address includes second bits for identifying a bank in said memory to be selected and then addressed by the first bits, whether incremented or not, of said address, said method comprising the steps of:

• incrementing said second bits when a carry output signal is generated to compensate for the incrementation of said first bits, and using said second bits, to select a bank in said memory.