Storage addressing error detection circuitry

Storage addressing error detection circuitry for a computer system including an addressable storage having at least one crossable logical boundary, a storage control unit connected to said storage and having an address register, a data register and control means for controlling the passing of an address from said address register to said storage, a central processing unit (CPU) having a CFU bus connected to said address and data registers of said storage control unit and having at least address register means for temporarily storing storage addresses, at least one I/O unit having an I/O bus connected to said address and data registers of said storage control unit, the improvement comprising:

• first hash generating means in said CPU for generating a hash value related to said logical boundary from addresses in said address register means and connected to said CPU bus for placing hash values thereon for transfer along with addresses from said address register means to said data register of said storage control unit to enable retrieval therefrom by said I/O unit,
• second hash generating means in said storage control unit for generating second hash values from non hash value portions of addresses entered into said address register of said storage control unit by said I/O unit, and
• error checking means connected to compare hash values in addresses entered into said address register of said storage control unit by said I/O unit with second hash values generated by said second hash generating means for generating an error signal for said I/O unit when a hash value in an address entered into said address register of said storage control unit by said I/O unit does not compare equal with a second hash value generated from that address.

In a computer system having an addressable main storage with at least one logical boundary therewithin, a storage control unit with at least an address register, a data register, and control means for controlling the passage of addresses to said main storage, a central processing unit (CPU) with at least address register means for temporarily storing main storage addresses and a CPU bus connecting said address register means to said address and data registers of said storage control unit, an I/O unit having at least an I/O bus connected to said address and data registers of said storage control unit, the improvement comprising:

• first I/O hash generate means connected to receive storage addresses from said address register means in said CPU to generate a hash value related to said boundary in said main storage and connected to concatenate said hash value with an address from said address register means and make said concatenated hash value and main storage address available to said I/O unit by entering said concatenated hash value and storage address into said data register of said storage control unit,
• second I/O hash generate means connected to said address register of said storage control unit to receive storage addresses therefrom and generate hash values, and
• error checking means connected to receive the hash value concatenated with a storage address from said I/O unit and entered into said address register of said storage control unit and compare it with hash values generated by said second I/O hash generate means and to generate an error signal when the comparison is unequal.

In a computer system having an addressable main storage with a plurality of logical boundaries therewithin, a storage control unit with at least an address register, a data register, and control means for controlling the passage of addresses to said main storage, a central processing unit (CPU) with at least address register means for temporarily storing main storage addresses and a CPU bus connecting said address register means to said address and data registers of said storage control unit, an I/O unit having at least an I/O bus connected to said address and data registers of said storage control unit, the improvement comprising:

• I/O hash generate means for generating hash values related to said logical boundaries, said I/O hash generate means being operable to generate hash values from addresses in said address register means for concatenation with those addresses where the concatenated hash value and address are entered into said data register of said storage control unit for transfer to said I/O unit and for generating hash values from the address portion of concatenated hash values and addresses entered into said address register of said storage control unit from said I/O unit, and
• error checking means for comparing the hash value concatenated with an addresses in said address register with the hash value generated by said I/O hash generate means from the address portion of the concatenated hash value and address in said address register and for generating an error signal upon an unequal comparison.