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US 4,903,114 AGranted
Resin-molded semiconductor
AssigneeFujitsu Limited
InventorsTsuyoshi Aoki, Michio Ono, Kazuhiro Maeda, Hiroyuki Kitasako
Life of this patent
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Abstract
A resin-molded semiconductor device applying an insulation plate unit mounted on a metal die-stage of a metal lead-frame. On the insulating plate unit, an integrated circuit semiconductor chips or a plurality of integrated circuit semiconductor chips are mounted and a plurality of relay-pads for relaying wire bonding connection between the semiconductor chip or chips and inner leads of the lead-frame are formed and arranged so as to correspond to the inner-leads, for electrically insulating the semiconductor chip or chips and the relay-pads from the metal die-stage.
Claims12
A resin-molded semiconductor device comprising:
- a metal lead-frame, comprising:
- a metal sheet die-stage located in a central portion of the semiconductor device and having an upper surface and a lower surface;
- and
- a plurality of inner-leads, each of said inner leads being a thin metal strip arranged on a plane parallel to and higher than an upper surface of said metal sheet die-stage, extending toward the central portion of the semiconductor device, and placed around said metal sheet die-stage forming a space therebetween;
- an insulating plate, mounted on said metal sheet die-stage having a bottom surface attached to the upper surface of said metal sheet die-stage and having an upper surface parallel to the bottom surface, comprising:
- a first surface formed at a central portion of said insulating plate;
- a second surface formed surrounding said first surface and being at a level, measured from the upper surface of said metal die-stage, higher than that of said first surface, said inner-leads being the same height as said second surface;
- and
- a plurality of relay-wirings provided along the periphery of said second surface, each of said relay wirings corresponding to each of said inner-leads;
- an integrated circuit semiconductor (IC) chip having an upper surface and a lower surface parallel to the upper surface, mounted on said first surface of said insulating plate and being the same height as said second surface, including a plurality of chip-pads formed on the upper surface of said integrated circuit semiconductor chip;
- a plurality of first bonding wires bonded between said chip-pads and said relay-wirings, respectively, said first bonding wires being short in length since said chip-pads and relay wirings are located a small distance from each other;
- and
- a plurality of second bonding wires bonded between said relay-wirings of said insulating plate and said inner-leads, each of said relay wirings being connected to said respective inner-leads, said metal sheet die-stage, a predetermined portion of said inner-leads, said insulating plate, and said second bonding wires being molded by a resin.
10 more elements
A resin-molded semiconductor device comprising:
- a metal lead-frame comprising:
- a metal sheet die-stage located at a central portion of the semiconductor device and having an upper surface and a lower surface;
- and
- a plurality of inner-leads, each being a thin metal strip arranged on a plane parallel to and higher than the upper surface of said metal sheet die-stage, extending toward the central portion of the semiconductive device, and placed around said metal sheet die-stage, forming a space therebetween;
- an insulating sheet mounted on said metal sheet die-stage;
- a printed wiring board, mounted on said metal sheet die-stage through said insulating sheet, having a bottom surface attached to said insulating sheet and an upper surface parallel to said bottom surface, said upper surface being separated into a plurality of first surfaces and a second surface that surrounds said first surfaces, said first surfaces being formed so that when measured from said bottom surface of said printed wiring board said first surfaces are lower than said second surface, said printed wiring board comprising:
- a plurality of relay-wirings formed along the periphery of said second surface, each of said relay-wirings corresponding to said inner-leads;
- a plurality of printed circuits placed on said second surface for electrically connecting one of integrated circuit (IC) semiconductor chips mounted on one of said first surfaces with the other of said integrated circuit semiconductor chips mounted on the other ones of said first surfaces;
- a plurality of IC chips mounted on said first surfaces respectively, each of said IC chips having a bottom surface and an upper surface, chip-pads being formed on the upper surface of each of said IC chips;
- and
- a plurality of first bonding wires for connecting between said chip-pads and said relay-wirings, respectively;
- and
- a plurality of second bonding wires for connecting between each of said relay-wirings and said inner-leads.
10 more elements
A resin-molded semiconductor device comprising:
- a metal lead-frame comprising:
- a metal sheet die-stage having an upper surface and a lower surface and located at a central portion of the semiconductor device;
- and
- a plurality of inner-leads each being a thin metal strip arranged on a plane parallel to and higher than the upper surface of said metal sheet die-stage, extending toward the central portion of the semiconductor device, and placed around said metal sheet die-stage, forming a space therebetween;
- an insulating sheet mounted on said metal sheet die-stage;
- a multi-layered printing wiring board, mounted on said metal sheet die-stage through said insulating sheet, having a bottom surface attached to said insulating sheet and an upper surface parallel to said bottom surface, said upper surface being separated into a plurality of first surfaces and a second surface surrounding said first surfaces, said first surfaces being formed so that the levels of said first surfaces, measured from the upper surface of said metal sheet die-stage, are equal to each other and lower than the level of said second surface, said multi-layered printed wiring board comprising:
- a plurality of relay-wirings formed along the periphery of said second surface, each of said relay-wirings corresponding to one of said inner-leads;
- a plurality of IC chips mounted on said first surfaces respectively, each of said IC chips including chip-pads formed on an upper surface of said IC chips;
- a plurality of printed circuits placed on said second surface for electrically connecting one of said plurality of IC chips mounted on one of said first surfaces with the other ones of said plurality of IC chips mounted on the other ones of said first surfaces;
- and
- a plurality of first bonding wires for connecting said chip-pads and said relay-wirings, respectively;
- and
- a plurality of second bonding wires for connecting between said relay-wirings and said inner-leads, respectively.
10 more elements
Dependencies are inferred from the claim text.