Architecture for high sampling rate, high resolution analog-to-digital converter system

A high sampling rate, high resolution analog-to-digital converter system comprising:

• a low speed, high resolution analog-to-digital converter for providing a first digital output signal in response to a system analog input signal;
• first sample and hold circuit means coupled to the input of said low speed analog-to-digital converter and operable at said low speed for sampling said system analog input signal;
• a high speed, low resolution pipelined analog-to-digital converter including second sample and hold circuit means operable at said high speed for sampling said system analog input signal, said high speed, low resolution analog-to-digital converter being adapted to generate address bits;
• memory means coupled to receive address bits from said high speed, low resolution analog-to-digital converter for generating a second digital output signal corresponding to said analog input signal and
• comparator means responsive to said first and second digital output signals for iteratively comparing said digital signals and being adapted to correct said second digital output signal by updating said memory means at said low speed rate said corrected second digital output signal thereby representing the high sampling rate, high resolution analog to digital converter system output signal.