US 4,903,015 AGranted

Communication device and star circuit for use in such a communication device, and device comprising such a star circuit

AssigneeU.S. Philips Corporation

InventorsBernard Van Steenbrugge, Egbertus J. Berkhoff

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Abstract

In a communication device with a star circuit all electrical bus connections are terminated by their characteristic impedance at the side of the stations as well as at the side of a star circuit. In order to enable arbitrary connection/disconnection of stations without modification of the terminating impedances while at the same time the termination remains optimum, each bus connection is provided with a separating element. This element receives an active bus connection state and communicates this state to all other connections so that the local bus connections are also activated. However, when a bus applied to the relevant separating element so that the latter cannot signal a further activation. Furthermore, for each connection there is provided a logic circuit in order to prevent the signalling of the own activation back to the own bus connection, while the inhibit signal for the own bus connection need not be active either.

Claims10

Dependent claims

A multi-master single-channel communication bus system having a star circuit for effecting communication between each one of a plurality of stations and each other of the plurality of stations, the star circuit comprising:

a plurality of bus line connections each including an associated electrical termination impedance (35, 36, 37) and an associated wired logic functionality, each bus line having a rest state and an active state,
said star circuit further comprising, for a first one of said connections:
(a) a respective buffer element (20,21,22) for storing said rest state of the bus line (bi1, bi2, bi3) connected to said first connection;
(b) a respective logic circuit (29, 30, 31);
(c) first respective interconnection means (26, 27, 28) for feeding logic circuits, associated with any connection other than said first connection, with a first signal (S1, S2, S3) representing the rest state of the bus line connected to said first connection;
(d) second respective interconnection means (32, 33, 34) for feeding the respective logic circuit of said first connection with a second signal (Q) representing absence of the rest state of the bus line connected to said first connection;
(e) respective means (b01, b02, b03) in said respective logic circuit for supplying:
(i) a first control signal, under control of either:
(A) presence of the second signal pertaining to said first connection, or
(B) combined presence of first signals analogous to said first signal and pertaining to all connections other than said first connection, and
(ii) a second control signal, otherwise;
and
(f) respective inhibiting means (23, 24, 25), fed by said respective supplying means, for:
(i) under control of said second control signal, inhibiting any change-of-state of said respective buffer element;
and
(ii) under control of said first control signal, allowing said change-of-state, and
wherein said second signal is fed to said wired logic functionality for masking said rest state by emulating said active state.

14 more elements

A star circuit for effecting communication between each one of a plurality of stations and each other of the plurality of stations in a multi-master, single-channel communication bus system, the star circuit comprising

(a) a plurality of bus connections for coupling with respective stations via respective bus lines, each bus line having a respective rest state and a respective active state;
(b) a plurality of terminating impedances, one for each bus connection;
(c) for each respective bus connection:
(I) a respective buffer element (20,21,22) for storing said rest state of the bus line (bi1, bi2, bi3) connected to the respective connection;
(II) a respective logic circuit (29, 30, 31);
(III) first respective interconnection means (26, 27, 28) for feeding logic circuits, associated with any connection other than the respective connection, with a first signal (S1, S2, S3) representing the rest state of the bus line connected to the respective connection;
(IV) second respective interconnection means (32, 33, 34), including respective logic circuit of the respective connection with a second signal (Q) representing absence of the rest state of the bus line connected to the respective connection;
(V) respective means (b01, b02, b03) in said respective logic circuit for supplying:
(i) a first control signal, under control of either:
(A) presence of the second signal pertaining to the respective connection, or
(B) combined presence of first signals analogous to said first signal and pertaining to all connections other than the respective connection, and
(ii) a second control signal, otherwise;
and
(IV) respective inhibiting means (23, 24, 25), fed by said respective supplying means, for:
(i) under control of said second control signal, inhibiting any change-of-state of said respective buffer element;
and
(ii) under control of said first control signal, allowing said change-of-state, and
wherein said second signal is fed to said respective wired logic functionality for masking said rest state by emulating said active state.

15 more elements

Dependencies are inferred from the claim text.