Extended range phase detector
AssigneeGeneral Signal Corporation
InventorDan H. Wolaver
Life of this patent
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Abstract
A linear three-state phase detector capable of accurately responding to simultaneous input signals has its linear range extended by uniquely sensing cycle slip and stepping a binary up-down counter. The cycle slip detector is capable of handling simultaneous inputs by determining that a resulting change of the three-state phase detector output occurs after a predetermined time after an input signal.
Claims21
A phase detector of n+1 cycle linear range whose output has a fundamental frequency at least as high as a fundamental frequency of its input signals comprising:
- first and second input means for receiving first and second input signals whose phase relationship is to be detected;
- three-state phase detector means connected to said first and second input means for producing state output signals representing lead, lag and center states as a function of the phase relationship of said first to said second input signals linearly over two cycles;
- cycle slip detector means connected to said first and second input means and said three-state phase detector means and responsive to said input signals and said state output signals for providing an up signal when said first input signal leads said second input signal by more than one cycle and a down signal when said first input signal lags said second input signal by more than one cycle;
- n-state up-down counter means connected to said cycle slip detector means for providing a count output as a function of said up and down signals;
- and
- output means connected to said up-down counter means and said three-state phase detector means for providing a phase output signal linear over n+1 cycles as a function of said count output and state output signals.
A phase detector of n+1 cycle linear range whose output has a fundamental frequency at least as high as a fundamental frequency of its input signals comprising:
- first and second input means for receiving first and second input signals whose phase relationship is to be detected;
- three-state phase detector means connected to said first and second input means for producing state output signals representing lead, lag and center states, as a function of the phase relationship of said first to said second input signals linearly over two cycles;
- cycle slip detector means connected to said first and second input means and said three-state phase detector means and including (a) lead means for providing an up signals when a first resulting change of output signals of said three-state phase detector means occurs after a predetermined time after said first input signal, indicating that said first input signal leads said second input signal by more than one cycle, and (b) lag means for providing a down signal when a second resulting change of output signals of said three-state phase detector occurs after said predetermined time after said second input signal, indicating that said first input signal lags said second input signal by more than one cycle;
- n-state up-down counter means connected to said cycle slip detector means for providing a count output as a function of said up and down signals;
- and
- output means connected to said up-down counter means and said three-state phase detector means for providing a phase output signal linear over n+1 cycles as a function of said count output and state output signal.
A phase detector of n+1 cycle linear range whose output has a fundamental frequency at least as high as a fundamental frequency of its input signals comprising:
- first and second input means for receiving first and second input signals whose phase relationship is to be detected;
- three-state phase detector means connected to said first and second input means for producing state output signals representing lead, lag and center as a function of the phase relationship of said first to said second input signals linearly over two cycles;
- cycle slip detector means connected to said first and second input means and said three-state phase detector means and responsive to said input and state output signals for providing an up signal when said first input signal leads said second input signal by more than one cycle and a down signal when said first input signal lags said second input signal by more than one cycle;
- n-state up-down counter means connected to said cycle slip detector means for providing a count output as a function of said up and down signals;
- and
- output means connected to said up-down counter means and said three-state phase detector means for providing a phase output signal linear over n+1 cycle and including (a) a first digital-to-analog converter for converting said count output to an analog count signal, (b) a second digital-to-analog converter for converting said state output signal representing lead, lag and center states into an analog phase detector signal, and (c) summer means for providing an analog sum of said analog count and phase detector signals.
As a phase detector comprising:
- first and second input means for receiving first and second input signals;
- three-state phase detector means connected to said first and second input means for providing a first and second phase signal output which define three stable states;
- cycle slip detector means connected to said first and second input means and said first and second phase signal outputs for providing an up signal when a first resulting change of a signal of said first phase signal output occurs after a predetermined time after said first input signal and a down signal when a second resulting change of signal of said second phase signal output occurs after said predetermined time after said second input signal;
- n-state up-down counter means connected to said cycle slip detector means for providing a count output as a function of said up and down signals;
- and
- output means connected to said up-down counter means and said three-state phase detector means for providing a phase output signal linear over n+1 cycles as a function of said count output and said first and second phase signal outputs.
A phase detector of n+1 cycle linear range whose output has a fundamental frequency at least as high as a fundamental frequency of its input signals comprising:
- first and second input means for receiving first and second input signals whose phase relationship is to be detected;
- three-state phase detector means connected to said first and second input means for producing state output signals representing lead, lag and center states, as a function of the phase relationship of said first to said second input signals linearly over two cycles;
- cycle slip detector means connected to said first and second input means and said three-state phase detector means and responsive to said input and state output signals for providing an up signal when said first input signal leads said second input signal by more than one cycle and a down signal when said first input signal lags said second input signal by more than one cycle;
- n-state up-down counter means connected to said cycle slip detector means for providing a count output as an m-bit digital word V as a function of said up and down signals;
- and
- output means connected to said up-down counter means and said three-state phase detector means for providing a phase output signal linear over n+1 cycles and including (a) converting means connected to said three-state phase detector means for converting said state output signals into an n-bit digital word P, (b) adder means connected to said counter means and said converting means for adding a most significant bit of said word P to a least significant bit of word V and for providing an m-bit digital output work Q, and (c) said phase output signal is output Q and P.sub.1, through P.sub.n-1.
Dependencies are inferred from the claim text.