Programmable logic arrays with each array column divided into a plurality of series connections of FETs

A programmable logic array comprising:

• a set of input terminals;
• a plurality of first FETs arranged in columns in matrix form, said first FETs in each column of said columns being programmably coupled with said input terminals at their gate terminals, each of said columns being divided into a plurality of series connections of said first FETs, each of said series connections being connected to a higher logic level through a second FET at one end and to a lower logic level at the other end;
• and
• a plurality of OR gates having their input terminals connected, respectively, to said one end of each of said series connections in order to produce, as an output of said logic array, the logical sum of the logical levels at said one end of each of said series connections belonging to each of said columns.