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US 4,902,915 AGranted
BICMOS TTL input buffer
AssigneeTexas Instruments Incorporated
InventorHiep V. Tran
Life of this patent
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Abstract
A threshold control BICMOS TTL input buffer is disclosed which substantially eliminates input trip point variation across power supply, process, and temperature and additionally minimizes buffer power dissipation.
Claims32
An input buffer comprising:
- a buffer input;
- an operational amplifier including an inverting input and a non-inverting input;
- a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input;
- a voltage source connected to said non-inverting input;
- a first stage inverter connected to said buffer input and including substantially identically sized field effect transistors as those of the threshold inverter, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter.
2 more elements
An input buffer comprising:
- a buffer input;
- an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower;
- a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input;
- a voltage source connected to said non-inverting input;
- a first stage inverter, connected to said buffer input, and including field effect transistors, the sizes of said first stage inverter's transistors being selected so that the gate to source voltage of a selected transistor from said first stage inverter is always below a predetermined voltage level, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter.
2 more elements
An input buffer comprising:
- a buffer input;
- an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower;
- a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input;
- a voltage source connected to said non-inverting input;
- a first stage inverter connected to said buffer input and including substantially identically sized field effect transistors as the threshold inverter, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter, the sizes of said field effect transistors of said first stage inverter and said threshold inverter being chosen such that the gate to source voltage of a selected transistor from said first stage inverter is always below a predetermined voltage level.
2 more elements
An input buffer comprising:
- a buffer input;
- an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower;
- a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input;
- a voltage source connected to said non-inverting input;
- a first stage inverter connected to said buffer input and comprising a p-channel transistor and an n-channel transistor, said p and n-channel transistors including a common drain connection and a common gate, connection said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter, the sizes of said field effect transistors of said first stage inverter and said threshold inverter being chosen such that the source voltage of said p-channel transistor is below a voltage level corresponding to a TTL logic level high plus the threshold voltage of said p-channel transistor.
2 more elements
Dependencies are inferred from the claim text.